10-04-2013, 03:29 PM
RAM 16X4 (IC 74189)
ABSTRACT:
To study and simulate design of RAM 16X4 using VHDL.
THEORY:
The R/W memory is made of registers that store bits of information. The no.of bits stored in a register is called a memory word. This memory is used as a writing pad to write user programs and data. The information stored in this memory can be read and altered easily.
PROCEDURE:
The RAM16X4 Design is entered through VHDL.
Simulate the design by applying test vectors-clk,en,rwbar,addr,datain and observing output dataout.
It is required to lock the pins and give timing constraints.
Implement the design by passing the design by various stages by mapping, time analysis and bit stream. For locking the pins write UCF file before implementation and guide the same through option set control files. Output of the implementation is .JED file, which can be directly programmed into target device FPGA.
The last step is programming in which the programme can physically download the architecture from computer to target device FPGA