18-08-2012, 04:53 PM
RISC Processor Development Laboratories
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Goal
The goal of this project is to walk you through the design and implementation of a 16-bit pipelined RISC microprocessor
that follows Computer Organization & Design. The overall project is broken into seven laboratories that
each can be easily accomplished in a two-week period. The laboratories have been designed to coincide and reinforce
the concepts covered during the lectures. The strategy of the laboratories is to minimize the complexity of
the overall CPU design by successively forming more complex components from earlier, smaller and simpler
components. Using this strategy, you will reach the final pipelined CPU in an orderly and easily achievable fashion.
This strategy also introduces a structured design approach in defining components and interfaces and an
orderly integration of simpler components into more complex components. In general, the laboratories follow
the bottom-up design approach followed in the textbook, starting with primitive components and then “gluing”
them together into a more complex set of subsystems and systems. The laboratories were originally based on
building the design under schematic capture and simulation. They have been redesigned and updated to allow
you to specify the design using VHDL.
Laboratory Descriptions
The seven laboratories are listed below. For each laboratory, you are encouraged to always consider cost versus
performance for your design. Understanding the basic cost versus performance trade-off familiar to practicing
designers is an important aspect of the process. This may be your first opportunity to engage in a moderately
complex design. It is emphasized that there are many solutions to any design, and your job is to balance cost versus
performance in each design. To support this basic philosophy, you can calculate a simple figure of merit,
#gates × execution time, for each project. If you are ambitious, this allows you to pursue more efficient or higher
performance implementations. A percentage of each laboratory grade is made competitive based on the reported
figure of merit. The objective of each laboratory is given in the table below.