09-08-2012, 05:00 PM
Realization of BCD adder using Reversible Logic
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INTRODUCTION
Everyday new technology which is faster, smaller and
more complex than its predecessor is being developed. The
increase in clock frequency to achieve greater speed and
increase in number of transistors packed onto a chip to
achieve complexity of a conventional system results in
increased power consumption. Almost all the millions of
gates used to perform logical operations in a conventional
computer are irreversible. That is, every time a logical
operation is performed some information about the input is
erased or lost and is dissipated as heat. As per Landauer [1],
for irreversible logic, each bit of information lost generates
kTln2 Joules of heat energy, where k is Boltzmann’s
constant and T is absolute temperature at which the
computation is performed. For room temperature T, the
amount of heat dissipated for one bit is small i.e. 2.9×10-21
J [2]. The current processors, first of all dissipate 500 times
this amount of heat every time a bit is lost.
PROPOSED CIRCUITS
The reversible logic implementation of conventional BCD
and carry skip BCD adder has already been proposed by
Himanshu et al [10]. In this paper, two adder schemes which
are faster in computing carry output are proposed. The
implemented reversible circuits are carry select BCD adder
and carry look-ahead BCD adder are discussed as follows.
A. Carry Select Scheme
The carry select scheme is better than the carry skip
scheme as it is faster in processing the result. In carry skip
scheme, carry is skipped only for a particular condition, i.e.
when either of the input is one. Therefore, the carry output
does not wait for each stage carry to propagate in ripple
fashion. The carry select scheme further reduces the delay
by selecting a pre-computed sum and carry outputs
depending on the carry-in.
RESULTS AND DISCUSSION
The RTL schematic diagram for carry select BCD adder
using reversible gate is shown in Fig.13 and its Xilinx ISE
9.2i simulated output is shown in Fig.14. The schematic
diagram for carry look-ahead BCD adder using reversible
gate is shown in Fig.15 and its Xilinx ISE 9.2i simulated
output
CONCLUSION
Computers today terribly waste energy and storage
capacity. They throw away millions of bits, billions of times
every second. These are based on irreversible logic devices,
which have been recognized as being fundamentally energyinefficient
for several decades. Truly, the only way we
might ever get around this limit is by using reversible
computing, which uncomputes bits that are no longer
needed, rather than overwriting them. Un-computing bits
allows their energy to be recovered and recycled for use in
later operation. Before the computer industry reaches the
fundamental brick wall of performance and energy
constraints of computing devices, reversible computing
needs to be fully developed.
This paper proposed novel designs of reversible BCD
carry select and carry look-ahead adders. The architecture is
designed specially to make them suitable for reversible logic
synthesis. The simulation of these circuits has been done
and they are ready to be used for designing large reversible
systems which is the necessary requirement of quantum
computers. These provide a base to build more complex
system like the BCD ALU of a primitive quantum CPU.