27-09-2013, 04:39 PM
Recursive Pseudo-Exhaustive Two-Pattern Generation
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Abstract
Pseudo-exhaustive pattern generators for built-in
self-test (BIST) provide high fault coverage of detectable com-
binational faults with much fewer test vectors than exhaustive
)-adjacent bit pseudo-exhaustive test sets,
2 binary combinations appear to all adjacent -bit groups of
inputs. With recursive pseudoexhaustive generation, all (
more than one modules can be pseudo-exhaustively tested in
parallel. In order to detect sequential (e.g., stuck-open) faults
that occur into current CMOS circuits, two-pattern tests are
exercised. Also, delay testing, commonly used to assure correct
circuit operation at clock speed requires two-pattern tests. In this
paper a pseudoexhaustive two-pattern generator is presented,
that recursively generates all two-pattern edge, this is the first time
in the open literature that the subject of
recursive pseudoexhaustive two-pattern testing is being dealt with.
A software-based implementation with no hardware overhead is
also presented.
INTRODUCTION
N CURRENT IC technology, highly complex chips have
low accessibility of internal nodes; this makes traditional
testing techniques costly and ineffective. Built-in self-test
(BIST) schemes have been proposed as a powerful alterna-
tive to external testing. BIST techniques employ on-chip test
generation and response verification; therefore the need for
expensive external testing equipment is reduced. Furthermore,
with BIST at-speed testing can be achieved; thus, the quality of
the delivered ICs is increased [1].
Exhaustive and pseudoexhaustive test generators provide
for complete fault coverage without the need for fault sim-
ulation or deterministic test pattern generation. Numerous
publications address the problem of pseudoexhaustive testing
as an alternative to competing schemes, e.g., exhaustive or
pseudorandom testing. Srinivasal et al. have posed bounds
on the length of pseudoexhaustive tests [2] and proposed
BIST pattern generators [3]. Chattopadhay proposed cellular
automata pseudoexhaustive test generators in [4].
Hardware Overhead
In order to calculate the hardware overhead of the proposed
generator, we have considered that a D-type flip-flop accounts
for eight gate equivalents and a XOR gate for four gate equiva-
lents. The implementation of the generic pseudoexhaustive two-
pattern generator requires the control module and the generic
counter. The recursive pseudoexhaustive generator additionally
requires the -stage counter and the -to- decoder. The hard-
ware overhead of the modules is presented in Table V.
CONCLUSION
Pseudoexhaustive test pattern generators provide very high
fault coverage without the need for fault simulation or determin-
istic test pattern generation. Various techniques have been pro-
posed for pseudoexhaustive test pattern generation for combi-
national faults. Adjacent bit pseudoexhaustive testing is mainly
targeted to data path architectures that have a strongly bit-orga-
nized character and contain internal buses that are partitioned
into physically adjacent lines [8].