19-02-2013, 10:40 AM
Reducing the computation time in(short bit width) 2’s complement multipliers
Reducing the computation.pptx (Size: 293.07 KB / Downloads: 21)
Abstract
Two’s complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage.
The proposed method is general and can be extended to higher radix encodings, as well as to any size square and m x n rectangular multipliers. We evaluated the proposed approach by comparison with some other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay.
Project Overview
Identify the Architecture From the literature survey
Model the Architecture into RTL [register transfer level]modeling
Verify the functionality of Modeled architecture in MODELSIM®
Synthesis the verified design in Xilinx ISE®
Generation of Bit map file for Dump into Spartan 3E FPGA
Program the Bit map file into FPGA.
Post simulation in ChipScope pro®.
Introduction
The MAC(Multiplier and Accumulator Unit) is used for image processing and digital signal processing (DSP) in a DSP processor.
The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing such as filtering, convolution, and inner products.
The MAC on specific processor cannot be run at 100% efficiency.
Conclusion:
Two’s complement n x n multipliers using radix- 4 modified booth encoding produce [N/2] partial product s but due to the sign handling , the partial product has a maximum height of [N/2]+1. we presented a scheme that produces a partial product array with maximum height of [N/2].