19-11-2012, 06:23 PM
Dynamical System Guided Mapping of Quantitative Neuronal Models onto Neuromorphic Hardware
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Abstract
We present an approach to map neuronal models
onto neuromorphic hardware using mathematical insights from
dynamical system theory. Quantitatively accurate mappings are
important for neuromorphic systems to both leverage and extend
existing theoretical and numerical cortical modeling results. In
the present study, we first calibrate the on-chip bias generators on
our custom hardware. Then, taking advantage of the hardware’s
high-throughput spike communication, we rapidly estimate key
mapping parameters with a set of linear relationships for static
inputs derived from dynamical system theory. We apply this
mapping procedure to three different chips, and show close
matching to their mapped neuronal models—the Jenson-Shannon
divergence was reduced to at least one tenth that of the shuffled
control. We confirm that our mapping procedure generalizes
to dynamic inputs: Mapped neurons match spike timings of
a simulated neuron with a standard deviation of 3.4% of the
average inter-spike interval.
QUANTITATIVE NEUROMORPHIC MAPPING
NEUROMORPHIC engineering aims to emulate computations
carried out in the nervous system by mimicking
neurons and their inter-connectivity in VLSI hardware [1].
Having succeeded in morphing visual [2], [3] and auditory [4],
[5] systems onto mixed-analog-digital circuits, engineers are
entering the arena of cortical modeling [6], [7], [8], [9]. This
is an arena in which neuromorphic systems’ parallel operation
and low energy consumption give them distinct advantages
over software simulation. Reproducing existing theoretical and
numerical cortical modeling results using the neuromorphic
approach will be facilitated by establishing quantitative links
between parameters of neural models and those of their
electronic analogs. Furthermore, this will build a foundation
for engineers to scale up neuromorphic models beyond the
limit of software simulators.
SILICON NEURON
The quadratic IF neuron uses a quadratic positive feedback
term to model the dynamics of voltage-gated sodium channels
[20]; it has become the model of choice for large software
simulations [21]. We analyze its bifurcation and spiking rate
using dynamical system theory, and show how to match these
dynamics in silicon.
Circuit
Neurogrid’s on-chip bias generator consists of a 12-bit
digital-to-analog current converter (modified from [24] to use
a RAM instead of a shift register) and an output gain stage
(Fig 4). The digital-to-analog converter (DAC) functions like
a PMOS “resistive” divider network [25] (Fig 4, top half). It
receives a proportional-to-absolute-temperature current, Imaster,
generated by a master bias circuit. Currents at each divider
node are then evenly split into two pathways of matching
impedances (2R) realized using identically sized transistors.
One of the pathways supplies the current to the next divider
while the other is to be selected for output. Ten control bits
and their complements (Fig 4, top grey area) either discard
splitter currents through Ires, or merge them into Idiv, which
feeds the output gain stages. In addition to the ten divider bits,
two current mirrors amplify Imaster by two and four times,
respectively. Their outputs, when selected, also merge into
Idiv, giving the DAC 12 bits of resolution. Idiv and Ires pass
into virtual grounds realized with a transconductance amplifier,
minimizing the mismatch.
Calibration
Since the DAC design has matured through wide usage in
the field [24], [25], the main objective for bias generators’
calibration is to extract div-gain values and characterize the
biasing transistors. A set of 106 bias generators are shared by
all 65,536 neurons on a Neurogrid chip. However, only one
bias generator’s voltage output is exposed to the outside for
calibration. Therefore, we assume the others have the same
calibration parameters, because bias generators are laid out in
close proximity.