16-08-2012, 12:04 PM
Nanosecond Delay Floating High Voltage Level Shifters
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Abstract
We present novel circuits for high-voltage digital level
shifting with zero static power consumption. The conventional
topology is analysed, showing the strong dependence of speed and
dynamic power on circuit area. Novel techniques are shown to
circumvent this and speed up the operation of the conventional
level-shifter architecture by a factor of 5–10 typically and 30–190
in the worst case. In addition, these circuits use 50% less silicon
area and exhibit a factor of 20–80 lower dynamic power consumption
typically.
INTRODUCTION
MODERN CMOS triple-well processes offer HV extensions
via special DMOS or drain-extended MOS
(hereafter simply referred to as DMOS) transistors and N-wells
that can float up to high voltages above the chip substrate. It is
common practice to place low voltage (LV) circuitry in these
floating wells and communicate between the various voltage
domains via DMOS cascodes, particularly for digital control
signals.
Improvement III – Fast Operation
In this section we describe how to dramatically improve the
switching speed of the level shifter. The circuit is shown in
Fig. 8. Here the simple cross-coupling of the level shifter has
been augmented by the insertion of two cascaded inverters in
each path. This effectively buffers and adds gain to the PDMOS
source voltage transitions, significantly increasing the gate drive
voltage on the pMOS pullup.
TEST CIRCUITRY AND RESULTS
The circuits described above are fast and run at high voltages.
The ultra-fast level shifter in particular has a delay of 2–4 ns. It
was not possible to bring the inputs and outputs directly to chip
IOs for stimulus and measurement as the speed of the IO drivers
themselves would have limited the test frequencies that could be
used. Even if the IO speed were sufficient, the power dissipation
involved in driving HV IOs at the required frequency would be
in the 200–400mWrange, causing thermal dissipation problems
for the test chip.
CONCLUSION
We presented a comprehensive analysis of the conventional
high voltage level shifter, showing the dependence of power and
speed on circuit area.We then showed an additive series of novel
techniques for simultaneously improving switching speed, silicon
area and power consumption as well as eliminating the
asymmetrical switching characteristic. These techniques are robust
to process variations and have been verified on silicon.