14-02-2013, 04:08 PM
Reviewing 4-to-2 Adders forB Multi-Operand Addition
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Abstract
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders
for the accumulation of partial products in multipliers, claiming one type to be superior to other
types. This paper analyses the use of various 3- and 4-element redundant digit sets for radix 2,
and compare their adder implementations using various encodings of the digits and carries. It is
shown that theoretically they are equivalent, and differences in their implementations need only be
very marginal. Another recent proposal for the use of the digit-set f0;12;3g, with a special 3-bit
encoding of digits, is analyzed and some optimizations are shown, including the possibility of using
a 2-bit encoding, simplifying the wiring of a multiplier tree. All these proposed designs are shown
to be equivalent to a standard 4-to-2, carry-save adder, except possibly for a few signal inversions.
Introdution
When implementing fast multipliers in VLSI, a major part of area and time is spent on accumulating
partial products using some kind of tree structures. Originally these were based on the use of
full-adders (and occasionally at the ends some half-adders), reducing the sum of three rows to the
sum of two rows, using either the Wallace- [17] or Dadda- organizations [2] of the tree structure.
As these structures are not very regular to lay out due to the 3-to-2 structure, it was suggested to
use 4-to-2 adders which allow the use of binary tree structures. [18] seems to be the first to propose
their use, based on the carry-save representation, where two addends are considered an encoding of
a single operand represented using the redundant digit-set f0;12g. Thus the 4-to-2 adder can be
considered an adder taking two such operands and adding them to produce the result in the same
representation. This addition can be performed in digit parallel, and thus in constant time, using an
array of such digit adders.