14-05-2014, 12:45 PM
Ripple Carry Adder
Ripple Carry .pdf (Size: 185.97 KB / Downloads: 363)
INTRODUCTION
The purpose of this project is to get familiarize us with design aspects of CMOS which is
being used in the industry for the last decade.
The main specification of the project is to design a binary 4 bit adder.
We design the required adder starting from logic gate level, go up to form the circuit
level & then draw the layout. The required integrity & specifications of the circuit can be
checked by simulation data to the circuit & to the required output.
Design of digital systems remains a very interesting & challenging field especially during
the last decade. With the development of various kind of design & simulation tools the
field is becoming more & more challenging & explore new ways of innovations.
Design 4 bit Binary Full Adder
Input two 4 bit numbers A & B. Output is 4 bit Sum and a Carry. We are allowed to use
any adder form, CRA, CLA and any logic form static, dynamic or variation of these or
within these families.
Optimize Performance Measure
Area (A), Time (T), Power (P) or AT2 are optimizing performance factors. We are given
flexibility to choose anyone of these to optimize our design.
Noise Margins: The noise margins should be at least 10% of the voltage swing.
Rise and Fall times: All input signals and clocks have rise and fall times of less than 500
psec. The rise and fall times of the output signals (10% to 90%) should not exceed 500
psec.
Load capacitance: Each output bit of the adder should have a 20 fF load.
Logic Design Procedure
A combinational circuit that performs addition of two bits is called a Half Adder. One
that performs addition of three bits (two significant and one last carry ) is called a Full
Adder. We develop Full bit Adder by means of hierarchical design. The Half Adder is
carried out first from which we develop the Full Adder. The procedure involves the
following steps:
• From the specifications of the circuit we will determine the required number of inputs
and outputs and assign a symbol to each.
• We will derive the truth table that defines the required relationship between inputs
and outputs.
• Obtain the simplified Boolean functions for each output as a function of the input
variables.
• Draw the logic diagram and verify the correctness of the design.
Transistor Sizing
For cascaded complementary structure, increasing the transistor sizes increases the
available (dis)charging current. But widening the transistors results in large parasitic
capacitors, which do not only effect propagation delay but also offer a larger load to the
proceeding gate. This technique only helps to a certain limit thereafter it defeat the
purpose. We thus determine to use this technique with extra “caution”.
For cascaded complementary structure, if Wn2=Wn1, we know that the delay is
minimum when Aspect Ratio N=Wp/Wn=Ur=square root(Un/Up); if Wn2 != Wn1, the
delay is minimum when Aspect Ratio N=Wp/Wn=square root(Ur*(1+2t)/(2+t)), where
t=Wn2/Wn1.
In order to minimize tcarry , we size the equivalent inverter of carry circuit as
Wp/Wn=square root(Un/Up) = 2. On the other hand, in order to offer minimum load
capacitance of the carry circuit, we size the equivalent inverter of sum circuit as
minimum size inverter.