26-05-2012, 01:18 PM
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits1
Runtime Mechanisms for Leakage Current.pdf (Size: 127.8 KB / Downloads: 38)
Introduction
The rapid increase in the number of transistors on chips has enabled
a dramatic increase in the performance of computing systems.
However, the performance improvement has been accompanied by
an increase in power dissipation; thus, requiring more expensive
packaging and cooling technology. Historically, the primary
contributor to power dissipation in CMOS circuits has been the
charging and discharging of load capacitances, often referred to as
the dynamic power dissipation. This component of power
dissipation is quadratically proportional to the supply voltage level.
Therefore, in the past, chip designers have relied on scaling down
the supply voltage to reduce the dynamic power dissipation.
Maintaining the transistor switching speeds requires a proportionate
downscaling of the transistor threshold voltages in lock step with
the supply voltage reduction. However, threshold voltage scaling
results in a significant amount of leakage power dissipation due to
an exponential increase in the sub-threshold leakage current
conduction. Borkar in [2] predicts a 7.5 fold increase in the leakage
current and a five-fold increase in total energy dissipation for every
new microprocessor chip generation.
Leakage Reduction by Increasing the Threshold Voltages
One way of decreasing the leakage current is increasing the
threshold voltages of transistors. There are several ways to do this,
but in all of them some process technology modification is
necessary. However, this may not be always possible. Another
approach is to use high-threshold voltage devices on non-critical
paths so as to reduce the leakage power while using low-threshold
devices on critical paths so that the circuit performance is
maintained. This technique requires an algorithm that searches for
the gates where the high-threshold voltage devices can be used
[11]. This technique has been called the Dual Vth CMOS. In
Dynamic Threshold MOS (DTMOS), the body and the gate of each
transistor are tied together such that when the device is off, the
leakage is low. If the device is on, then the current will be high
[13]. Among the techniques that dynamically modify the threshold
voltage during runtime, the classic example is Standby Power
Reduction (SPR) or Variable Threshold CMOS (VTCMOS). In this
method Vth is raised during the standby mode by making the
substrate voltage either higher than Vdd (for P transistors) or lower
than ground (for N transistors).
Leakage Reduction by Gating the Supply Voltage
The last approach considered is power supply gating. There are
many ways in which this technique can be implemented, but the
basic idea is to shut down the power supply so the idle units do not
consume any power. This can be done using some high threshold
transistors called sleep transistors [1]. If the threshold voltages of
sleep transistors are changed at runtime, the triple-well technology
is required. Another possibility is to use Multiple-Threshold
Voltage CMOS (MTCMOS) [10]. In MTCMOS, a high threshold
device is inserted in series with low threshold transistors creating a
sleep transistor. This creates virtual supply and ground rails whose
voltage levels are very close to the real supply and ground lines
because of the very small on-resistance of the inserted high-Vth
transistors. In practice, only one virtual rail (usually the virtual
ground) is used. Normally, one sleep transistor per gate is used, but
larger granularities are possible, which require fewer transistors.
The problems with this technique are reduced performance and
noise immunity.
Leakage Minimization by Input Vector Control
By applying a minimum leakage vector (MLV) to a circuit, it is
possible to decrease the leakage current of the circuit when it is in
the standby mode. We assume that the environment in which the
circuit is placed e.g., with the aid of a power management unit,
generates a SLEEP signal for the circuit. This signal is then used to
initiate the application of the MLV to the circuit inputs. To use this
method for leakage reduction, it is necessary to find an input vector
that causes the minimum leakage current in a VLSI circuit. A
trivial lower (upper) bound on the leakage current is the sum of the
minimum (maximum) leakage currents of all logic gates in the
circuit. However, this may not correspond to any feasible solution
because the input combination that produces the minimum
(maximum) leakage in some gate, gatei, may conflict with the one
that produces the minimum leakage for another gate, gatej. In the
remainder of this section, we describe an algorithm for finding an
MLV for a given combinational logic circuit. More precisely, given
a combinational logic circuit description, we first construct a
Boolean network, which computes the total leakage of that circuit.