13-08-2013, 03:14 PM
VHDL for COE-608 Overview
VHDL for COE-608 .pdf (Size: 327.36 KB / Downloads: 71)
Modeling Digital Systems
• VHDL is for writing models of a system
• Reasons for modeling
requirements specification
documentation
testing using simulation
formal verification
synthesis
Modeling Behavior
• Architecture body
– describes an implementation of an entity
– may be several per entity
• Behavioral architecture
– describes the algorithm performed by the module
– contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
Modeling Structure
• Structural architecture
– implements the module as a composition of subsystems
– contains
• signal declarations, for internal interconnections
– the entity ports are also treated as signals
• component instances
– instances of previously declared entity/architecture pairs
• port maps in component instances
– connect signals to component ports
• wait statements
Mixed Behavior and Structure
• An architecture can contain both behavioral and
structural parts
– process statements and component instances
• collectively called concurrent statements
– processes can read and assign to signals
• Example: register-transfer-level model
– data path described structurally
– control section described behaviorally
Test Benches
• Testing a design by simulation
• Use a test bench model
– an architecture body that includes an instance of the
design under test
– applies sequences of test values to inputs
– monitors values on output signals
• either using simulator
• or with a process that verifies correct operation
Regression Testing
• Test that a refinement of a design is correct
– that lower-level structural model does the same as a
behavioral model
• Test bench includes two instances of design under
test
– behavioral and lower-level structural
– stimulates both with same inputs
– compares outputs for equality
• Need to take account of timing differences
Elaboration
• “Flattening” the design hierarchy
– create ports
– create signals and processes within architecture body
– for each component instance, copy instantiated entity
and architecture body
– repeat recursively
• bottom out at purely behavioral architecture bodies
• Final result of elaboration
– flat collection of signal nets and processes
Simulation
• Execution of the processes in the elaborated model
• Discrete event simulation
– time advances in discrete steps
– when signal values change—events
• A processes is sensitive to events on input signals
– specified in wait statements
– resumes and schedules new values on output signals
• schedules transactions
• event on a signal if new value different from old
value
Simulation Algorithm
• Simulation cycle
– advance simulation time to time of next transaction
– for each transaction at this time
• update signal value
– event if new value is different from old value
– for each process sensitive to any of these events, or
whose “wait for ...” time-out has expired
• resume
• execute until a wait statement, then suspend
• Simulation finishes when there are no further
scheduled transactions