10-10-2012, 11:51 AM
SEQUENTIAL CIRCUIT DESIGN GUIDELINES
Sequential Circuit Design Guidelines.ppt (Size: 841.5 KB / Downloads: 30)
Introduction
The Design Guidelines constitute a general set of recommendations intended for use by designers.
The guidelines are independent of any particular EDA tool or silicon process.
They are applicable to Gate Arrays, Cell-Based ASICs (CBICs) and full-custom designs.
Synchronous Circuits
A synchronous circuit is one in which:
All data storage elements are clocked, and in normal operation change state only in response to the clock signal
The same active edge of a single clock signal is applied at precisely the same point in time at every clocked cell in the device
Double-edged clocking
The two flip-flops are clocked on opposite edges of the clock signal. This makes synchronous resetting and test methodologies such as scan-path insertion difficult, and causes difficulties in determining critical signal paths.
Recommended Circuits
Methods of achieving the requirements of synchronous
design, and avoiding the non-recommended situations
described above are dealt as follows:
Synchronous clocking by means of clock buffering
Flip-flop driving clock signal of another flip-flop
System clock generation
Asynchronous resets.
Clock Buffering
To achieve the requirement of a simultaneous application of a single clock signal at all storage elements in a design, and avoid problems due to fanout, a clock buffering scheme needs to be implemented consistently throughout a circuit.
Excessive clock fanout
Excessive clock fanout leads to slow clock edges, which can cause a number of problems, including an increased risk of metastability in flip-flops which capture external asynchronous signals.
Recommended Circuits
The recommended clock buffering scheme is balanced tree
buffering, which must satisfy the following conditions:
1. The same depth of buffering to all clocked cells
2. The same fanout on all buffers. This must be checked after placement and routing, to ensure that tracking capacitances do not unbalance the fanout.
3. Lightly loaded buffers to keep clock edges sharp. An alternative is to use a combination of geometric and tree buffering)
Clock Bar Cells
The use of clock bar cells for clock distribution from within a standard cell area is recommended.
A single Clock bar cell, positioned correctly in the centre of the standard cell area, can provide a balanced clock net distribution.
This runs a vertical clock trunk through the middle of the cell area, allowing clock net branches to feed cells on either side of the trunk.
This method reduces the risk of clock skew by halving the effective clock path length along a row of cells, compared with a clock supplied from one end of the cell row.