11-04-2012, 10:40 AM
SHARC LINK PORTS
SHARC LINK PORT.ppt (Size: 58.5 KB / Downloads: 56)
Harvard Architecture :
Program memory can store data.
Able to simultaneously read or write data at one location and get instructions from another place in memory.
2 buses:
Data memory bus.
Program bus.
Either two separate memories or a single dual-port memory.
Super Harvard Architecture:
Many processor employ Harvard Architecture by having two separate memories or caches integrated into the processor chip
The SHARC is unique in that it’s internal memory is capable of holding a large program as well a large amount of data. This is what makes it Harvard Architecture SUPER
DSP (Digital Signal Processor)
High speed, low overhead data movement and rapid computations required.
Usually has a small on-board ROM, RAM and single cycle multiply.
Designed to run single line, serial in, serial out, signal processing applications very
fast.
The inner product of two vectors is a common computation for determining energy or correlation.
The process which has the lowest instruction time will have the best performance.
SHARC DSP
The SHARC incorporates features aimed at optimizing such loops.
High-Speed Floating Point Capability
Extended Floating Point
These features are DSP specific.
Meaning, when applied to a non-DSP application performance may not be as optimal.
It also has some features not related directly to optimizing numeric computations.
Pipelining
Handling Branches
Zero Overhead Looping on the SHARC
A single instruction outside the loop performs loop set-up. Informing the SHARC that there is a loop approaching.
The instruction also includes the iteration count and termination condition.
This causes the pipeline to remain full during loop execution and also allows the termination condition to be tested in parallel.
Multi-processing Architectures
Cluster Design:
Groups of up to 6 in a cluster.
Most common for joining multiple SAHRC.
All processors, global I/O and global memory connected to a common “Cluster bus.”
Each SHARC can “drive” the bus.
Mesh Design:
All SHARC joined by their link ports and are connected to a common bus.
In SIMD mode one single master SHARC drives the bus.
In MIMD mode mesh architecture cannot function if data is lager then on chip available memory.
Advantageous scalability over a wider range of applications.