04-12-2012, 05:40 PM
SMART GRID
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INTRODUCTION
The main idea of this project pertains to the reliable and continuous power supply to the customers and optimizing the power distribution among various areas based on power demand.
There are severe power cuts; especially in rural areas in summer season (typically 6 to 8 hours).This is actually done in the following way.
Whenever the power given to the substation is not sufficient to meet the power demand of all the areas under a given substation, some areas are given power for a given period and the other areas are under power-cut. This schedule is made alternatively for the areas in the given substation to meet the incoming power demand.
We developed a technology that is to be installed in homes which are interconnected. Communication between houses, lanes and to the substation is automatic. Each consumer is allowed to be given the minimum power required for basic loads like fans and lights, instead of power cut during this period.’
SMART GRID TECHNOLOGY
A smart grid is a digitally enabled electrical grid that gathers, distributes, and acts on information about the behavior of all participants (suppliers and consumers) in order to improve the efficiency, importance, reliability, economics, and sustainability of electricity services
Metering of electricity consumption was necessary on a per-user basis in order to allow appropriate billing according to the level of consumption of different users. Because of limited data collection and processing capability during the period of growth of the grid, fixed-tariff arrangements were commonly put in place, also commonly dual-tariff arrangements where night-time power was charged at a lower rate that daytime power. The motivation for dual-tariff arrangements was the lower night-time demand.
Opportunities to take advantages of improvements in electronic communication technology to resolve the limitations and costs of the electrical grid have become apparent. Technological limitations on metering no longer force peak power prices to be averaged out and passed on to all consumers equally. In parallel, growing concerns over environmental damage from fossil-fired power stations has led to a desire to use large amounts of renewable energy. Dominant forms such as wind power and solar power are highly variable, and so the need for more sophisticated control systems became apparent, to facilitate the connection of sources to the otherwise highly controllable grid.
POWER SUPPLY CIRCUIT:
The 5V power supply circuit of fig 3.1 consists of a step down transformer. 230V AC is applied to the primary side of the transformer and the voltage obtained on the secondary side is 9V AC. The 9V AC is converted to DC using a bridge rectifier comprising of four 1N4007 diodes. The capacitors are used for the removal of ripples in the circuit. The voltage regulator used is LM7805 which produces a steady 5V regulated DC.
Optocoupler :
The MOC3041 device consists of gallium arsenide infrared emitting diodes optically coupled to a monolithic silicon detector performing the function of a Zero Voltage Crossing bilateral triac driver. They are designed for use with a triac in the interface of logic systems to equipment powered from 115 Vac lines, such as solid–state relays, industrial controls, motors, solenoids and consumer appliances, etc.
Current Transformer :
Current Transformers are used to find the line current . We can measure high value of currents by stepping down to a small value. The primary terminals of the CT are connected in series with the load. The equivalent voltage is obtained by connecting a resistor across the ct secondary terminals.
SOFTWARE USED:
In the microcontroller based equipment, the hardware works only when the relevant software is written into the ROM area of the micro controller. Whenever the power is switched on to the microcontroller, the CPU runs the specified program and generates the relevant outputs to control the internal and external peripheral devices to accomplish the required task.
AVR CPU Core:
The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
In order to maximize performance and parallelism, the AVR uses Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect addresses register pointers for Data Space addressing – enabling efficient address calculations. One of the address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-register, Y-register, and Z-register, described later in this section.
SRAM Data Memory:
Figure 3 shows how the ATmega16 SRAM Memory is organized. The lower 1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next1024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
Configuring the Pin:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
External Interrupts:
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. If enabled, the interrupts will trigger even if the INT0...2 pins are configured as outputs. This feature provides way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. INT2 is only an edge triggered interrupt. This is set up as indicated in the specification for the MCU Control Register – MCUCR – and MCU Control and Status Register – MCUCSR. When the external interrupt is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low.