21-09-2013, 01:07 PM
DESIGN OF HAMMING CODE USING VERILOG HDL
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Hamming code is an error-
correction code that can be
used to detect single and
double-bit errors and correct single-bit
errors that can occur when binary data
is transmitted from one device into an-
other.
This article presents design and de-
velopment of (11, 7, 1) Hamming code
using Verilog hardware description
language (HDL). Here, ‘11’ corre-
sponds to the total number of Ham-
ming code bits in a transmittable unit
comprising data bits and redundancy
bits, 7 is the number of data bits while
‘1’ denotes the maximum number of
error bits in the transmittable unit. This
code fits well into small field-program-
mable gate arrays (FPGAs), complex
programmable logic devices (CPLDs)
and application-specific integrated cir-
cuits (ASICs) and is ideally suited to
communication applications that need
error-control.
Error correction
Use of simple parity allows detection
of single-bit errors in a received mes-
sage. Correction of these errors re-
quires more information, since the po-
sition of the corrupted bit must be
identified if it is to be corrected. (If a
corrupted bit can be detected, it can
be corrected by simply complement-
ing its value.) Correction is not pos-
sible with one parity bit since any bit
error in any position produces exactly
the same information, i.e., error. If
more bits are included in a message,
and if those bits can be arranged such
that different corrupted bits produce
different error results, then corrupted
bits could be identified.
Verilog HDL
program
Verilog is a general-purpose
hardware description lan-
guage that is easy to learn and
use. It is similar in syntax to
the ‘C’ programming lan-
guage. Verilog allows differ-
ent levels of abstraction to be
mixed in the same model.
Thus a designer can define a
hardware model in terms of
switches, gates, register trans-
fer level (RTL) or algorithmic/
behavioural code. Verilog
should not be confused with
VHDL, which is yet another
HDL whose first letter stands
for ‘very high-speed inte-
grated circuit’ (VHSIC).
Testing procedure
Fig. 2: Redundancy bits calculation
Fig. 3: Example of redundancy bits calculation
Verilog HDL
program
Verilog is a general-purpose
hardware description lan-
guage that is easy to learn and
use. It is similar in syntax to
the ‘C’ programming lan-
guage. Verilog allows differ-
ent levels of abstraction to be
mixed in the same model.
Thus a designer can define a
hardware model in terms of
switches, gates, register trans-
fer level (RTL) or algorithmic/
behavioural code. Verilog
should not be confused with
VHDL, which is yet another
HDL whose first letter stands
for ‘very high-speed inte-
grated circuit’ (VHSIC).