15-02-2013, 04:04 PM
SRAM Based Re-programmable FPGA tbr Space Applications
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Abstract
An SRAM (static random access memory)-based reprogrammable
FPGA (field programmable gate array) is
investigated for space applications. A new commercial
prototype, named the RS family, was used as an example for
the investigation. The device is fabricated in a 0.25p, m CMOS
technology. Its architecture is reviewed to provide a better
understanding of the impact of single event upset (SEU) on
the device during operation. The SEU effect of different
memories available on the device is evaluated. Heavy ion test
data and SPICE simulations are used integrally to extract the
threshold LET (linear energy transfer). Together with the
saturation cross-section measurement from the layout, a rate
prediction is done on each memory type. The SEU in the
configuration SRAM is identified as the dominant failure
mode and is discussed in detail.
INTRODUCTION
The antifuse FPGA has gained significant visibility in
recent years as the programmable logic device choice for
space applications. The antifuse switch is nonvolatile and
insensitive to both single event and total dose effects.
Compared to mask-wired ASICs (application specific
integrated circuits), it has the advantage in turnaround,
flexibility, and (hardware) cost per design, while maintaining
the same radiation performance. However, there has been a
tremendous interest in re-programmable FPGAs for the
potential realization of a "re-programmable satellite" in the
future. There are two re-programmable FPGA technologies in
the market right now. One uses a FLASH/EEPROM
(electrically erasable programmable read only memory)
configuration switch and the other an SRAM switch. This
paper will focus on the SRAM-based technology only. The
development and radiation effects for FLASH-based FPGAs
will be published elsewhere (see reference [ 1]).
CSRAM SEU
CSRAM is a five-transistor SRAM, designed for fast read
and small die area. Since the N-well (P-substrate) process is
used, the N+ junctions (N-hit) are more vulnerable than P+
junctions (P-hit). The upset of any one CSRAM bit
potentially will cause a functional failure at the device level.
This functional failure is considered soft if the errors in
CSRAM configuration are corrected quickly. The simplest
error correction approach is to reload the configuration states
from an uncorrupted storage.
There are potential high current modes in the device due
to CSRAM SEU. For example, when two inverter outputs
with different states are connected erroneously due to the
CSRAM upset (Figure 4), there is a static current through
transistors and interconnects from Vcc to GND. This situation
is close to a micro-latch-up. However, the current is through
well-designed transistors while latch-up occurs in parasitic
structures. A permanent damage in metallization, for
example, is unlikely.
SEU IN MEMORIES
A. Heavy 1on Testing Results and SPICE Simulation
In the SPICE simulator, the heavy ion effect is modeled
by injecting a hit current pulse at the (reverse-biased) active
junctions. This current pulse is of a triangular shape with rise
time and fall time equal to lOOps. The injection node is
clamped to either GND or Vcc by a variable capacitor during
charge collection. This method assumes the hit pulse is much
faster than the circuit response and ignores the detailed timing
information carried in the pulse shape. It is the-worst-casedesign
simulation to generate a relatively conservative critical
charge for SEU. The resulting critical charge (Qtrit) is an
approximation of the Qsis (the charge significant to the upset
process) in reference [5].
SEU Rate Prediction
To evaluate the radiation tolerance at the device level, the
upset rate of each memory type is calculated using Space
Radiation 4.0. The space environment is the Geosynchrous
orbit with the solar minimum condition. Spacecraft shielding
is assumed as 100mil aluminum.
For device parameters, the LET is converted from Qcrit by
equation 1. The saturation cross section is measured from the
layout design. The Weibull shape of 2 and width of 10MeVcm2/
mg are assumed. These numbers are believed to be
conservative based on the fact that there are several active
junctions in every single event, and also from previous heavy
ion test data on Actel FPGA devices. Usually much more
gradual Weibull curves were measured.