27-02-2013, 03:09 PM
STT RAM
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ABSTRACT
We present a design space feasibility region, as function of MTJ characteristics and target memory specification, to explore the design margin of 1T-1MTJ memory cell for STT RAM. The spin transfer torque random access memory become a promising technology for feature computing system for its fast access time, high density, non-volatility and small write current. STT RAM suffers from process variation and temperature fluctuations, which significantly affect the performance and stability of magnetic tunnelling junction device. A non-volatility memory utilizes the Rashba spin orbit coupling too write data on a free ferromagnetic layer and uses tunnelling magneto-resistive effect for data read back. In STT RAM the temperature fluctuation can significantly affect characteristics of both magnetic and electric devices.
Data from measured devices are used to model the statistical variation of MTJ critical switch current and resistance. The sensitivity of design space to analyzed for the scaling of both MTJ and underlying transistor technology. A hybrid CMOS/nano-meter technology reconfigurable architecture earlier, it used the concept of temporal logic folding and fine grains dynamic reconfiguration to increase logic density by order of magnitude. The design flow is proposed to optimize design margin for Giga bit scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible CMOS technologies for 90-, 65-, 45-, and 32-nm process, predictive technology models are used to explore the feature scalability of STTRAM in upcoming 22 nm and 16 nm technology. To achieve flash-like density (<6F2) is advanced CMOS technologies, aggressive scaling of critical switch current density will be require.
INTRODUCTION
The MRAM utilizes the both spin and charge properties of electrons. MRAM has attractive properties of non-volatile consumption, and virtually unlimited read- write endurance. MRAM have attracted significant amount of interest as commercial variable universal memory technology, with the density of DRAM, the speed of SRAM and non-volatility of flash RAM.
The first generation of MRAM used field induced magnetic switching to toggle the MTJ between its parallel and Antiparallel state. FIMS works by organize word and bit line into a cross point architecture. Synchronized pulse of current is applied to the desired word and bit line. The non-volatility storage element of MRAM is the MTJ.
Structurally an MTJ is a pair of ferromagnetic separated by thin insulating layer. Data storage is achieved by exploiting the magnetic orientation of the ferromagnetic layer. The parallel configuration leads to a low resistive state Rp, anti-parallel configuration leads to a high resistive state RAP. The tunnel magneto resistive is the difference between the Rp and RAP, TMR is a metric for the determine the efficiency of the spintronic operation of an MTJ. The TMR is defined as
TMR=Rp- RAP/Rp.
To control the magnetization reversal with electrical current is to use the Rashba spin torque. I.e. spin orbit coupling effect that couples the spin of the electron to its momentum. Spin transfer torque switching that utilizes the spin polarized current. The switching method was first proposed in 1996. And boast the advantage of low power consumption and reduce risk of cross- writing compared with the conventional method. Strongly magnetic fields can MTJ to switch to the designed state. A small access transistor is acquire to read state suffering from a write disturbance problem, this is the main drawback, so we have to introduced a new STT RAM for increase the write current as technology scale.
Spin transfer torque random access memory is based on the magnetization programming of magneto tunnelling junction. The area of the STT-Ram cell is determined by the NMOS transistor size, which must be sufficiently large to supply enough write current to the MTJ.
A hydride COMS/ nano-technology reconfigurable architecture, called NATURE. The NATURE is based on CMOS logic and high speed, high density nano RAMs. The migration trend of microprocessor to multi core architecture generates explosive demand of on chip embedded memory. SRAM, DRAM and etc.. face significant scaling challenges 45 nm technology nodes and beyond. The scalability of STT-RAM technology is guaranteed by the fact that magnitude of switching current is proportional to the MTJ cell area.
STT RAM operating in the temperature range from 300 to 375 K, our simulation show sense margin decreases from 28 to 21 mV and they require write pulse width need increase from 11.2 to 13.7 ns by using 90-, 65-, and 45- nm. In feature we are require to develop by using 22 nm and 16 nm technology.
The design space of 1T-1MTJ memory cell for STT RAM, we use a processional-based switching model, modified to include thermally activated switching, to capture the dynamic nature of the MTJ. The effect of both CMOS and MTJ device variability across process-voltage-temperature (PVT), which is notably absent in prior work, are demonstrated with our analysis. These effects are used to characterize STT RAM that scale down to a 32 nm technology with measured device data and extrapolated down to 16 nm using predictive technology models (PTM).
PROCESS VARIATION AND ENVIRONMENTAL FLUCTUATION MODELLING MTJ VARIABILITY AND SCALING
MTJ is composed of two ferromagnetic layers, i.e., reference layer and free layer, and one oxide barrier layer e.g., MgO. The magnetization direction of reference layer is fixer and while the magnetization direction of free layer can be changed by a switching current polarization by the magnetization of reference layer. When the magnetization directions of the two ferromagnetic layers are parallel, MTJ is at low state, when the magnetization directions of the two ferromagnetic layers are anti parallel, MTJ is at high state.