04-10-2012, 10:58 AM
Multilevel inverter topologies with reduced power circuit complexity for medium voltage high power induction motor drives
Multilevel inverter topologies.ppt (Size: 7.4 MB / Downloads: 108)
Advantages of Multilevel inverters over two-level inverter
Devices of lower rating can be used thereby enabling the schemes to be used for high voltage applications.
Reduced total harmonic distortion (THD).
Since the dv/dt is low, the EMI from the system is low.
Lower switching frequencies can be used and hence reduction in switching losses.
Disadvantages of multilevel inverters
The number of isolated DC-links are more compared to a two-level inverter.
Neutral point voltage variations.
Power bus structure and hence the control schemes become complex as the number of levels increases.
Decrease in Reliability
Effect of common mode voltage
PWM inverters generate high frequency and high amplitude common mode voltages, which induces ‘shaft voltages’ on the rotor side.
When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents
This causes premature failure of the motor bearings and also poses EMI issues.
In open end winding configuration, isolated DC links are needed to avoid heavy currents due to the common mode voltages in the phase windings.
The best solution for all these is to eliminate the CMV itself.
Motivation for the Proposed scheme
Even after the selective switching for the common mode voltage elimination, the three-level structure have higher multiplicity in the switching states compared to the conventional NPC three-level inverter without CMV elimination.
This suggests that some optimization is possible in the power circuit.
Salient features of the drive schemes
Only 18 switches are needed for a CMV eliminated 3-level drive scheme compared to the previous configuration which has 24 switches.
CMV is eliminated in the entire modulation range upto 6 step mode.
Only two isolated dc-links are needed.
An SVPWM algorithm which uses only sampled amplitude of the reference signals for switching time computation is used which makes the implementation faster compared to the conventional methods.