14-09-2013, 12:59 PM
SYNTHESIZING HARDWARE FROM A VERILOG DESCRIPTION
HARDWARE FROM A VERILOG .pdf (Size: 1.32 MB / Downloads: 36)
Introduction
We have been using the HDL Verilog to model digital circuits. Verilog behavioral code
is used to model the devices (gates) in the circuit and Verilog structural code is used to
describe how the devices in the circuit are connected together. Simulation with this kind of
model allows us to accurately simulate both logic and timing of a digital circuit. The Verilog
code is a complete description of the behavior of our circuit.
Modeling circuits with Verilog code leads us to an interesting idea. Since the Verilog
code accurately describes the circuit, can we reverse the process and determine the circuit
from the Verilog code description? The answer to this question is yes. The process of creating
a digital circuit from a coded description is called synthesis. Synthesis has become the
preferred method for modern digital design.
Modern digital designs are seldom built using discrete devices. They are programmed
into Programmable Logic Devices (PLDs) such as Programmable Array Logic (PALs), Complex
Programmable Logic Devices (CPLDs), or Field Programmable Gate Arrays (FPGAs), or they
are custom fabricated into a single silicon chip. The custom fabrication must be done at a
foundry. Designs which are fabricated at a foundry are called Application Specific Integrated
Circuits (ASICs)
Application Specific Integrated Circuits (ASICs)
Integrated circuits are circuits which are built on a single silicon chip. Discrete device
are actually small integrated circuit. They contain a number of transistors (the basic building
blocks of digital circuits) on a single silicon chip. ASICs have a large number of transistors on a
single chip. In fact, ASICs have so many transistors, we use a larger design block called a
standard cell as the basic building block. Figure 6.2-1 shows an enlarged drawing of an ASIC
chip. The two large gray areas are standard cell areas (one on the left and one near the
middle). They contain hundreds of standard cells in rows across the area. (This picture does
not attempt to show the detail in the standard cell areas.) The other gray blocks are memory
blocks. We will look at memory later in the text. Special input and output cells with pads for
connecting to the device pins are placed around the periphery. In some parts of the chip,
individual connecting traces are seen as gray lines. In other parts of the chip, such as around
the periphery, the traces are so dense they merge into a solid gray area.
Programmable Array Logic (PAL) Devices
PALs, which were once manufactured in a large variety of configurations, are now
manufactured in only a few. These few configurations are mostly the so called “versatile” PALs
designated with the letter V in their type designation. Figure 6.6-1 shows the block diagram for
one of the versatile PALs (the ispGAL22V10 from Lattice). The type designation 22V10
generally means that there are a total of 22 input, I/O, and output pins and 10 logic circuits.
This device consists of eleven dedicated inputs, ten and-or logic circuits which are contained in
the block of the diagram labeled programmable and array, ten output macrocells which are
also programmable, a clock input which can also be used as a logic input, and ten outputs
which can also be used as I/Os, or as dedicated inputs (Q) depending on the programming of
the output macrocells. The PAL22V is by far the most commonly used simple PAL, and is the
only one we will use in our examples. The ispGAL22V10 is not exactly a generic 22V10. It has
the same architecture as the 22V10 but has a circuit for in system programming. This circuit is
labeled Programming Logic on the block diagram. It makes use of a serial input to the device.
The serial input, which is described in an IEEE standard (usually called JTAG), was originally
designed for automatic circuit board testing, but has been extended so it can be used to load
the programming information into programmable devices. We will use this device for our
examples since Lattice furnishes a synthesis program which targets this device.