14-07-2012, 01:38 PM
SANDY BRIDGE SPANS GENERATIONS
Microprocessor-Reportseminar-Sandy-Bridge.pdf (Size: 3.41 MB / Downloads: 112)
Integration Boosts Graphics Performance
Intel had a false start with integrated graphics: the ill-fated
Timna project, which was canceled in 2000. More recently,
Nehalem-class processors known as Arrandale and Clarkdale
“integrated” graphics into the processor, but these
products actually used two chips in one package, as Figure
1 shows. By contrast, Sandy Bridge includes the GPU on
the processor chip, providing several benefits. The GPU is
now built in the same leading-edge manufacturing process
as the CPU, rather than an older process, as in earlier
products.
AVX Widens FPU to 256 Bits
As announced by Intel in 2008, AVX is a new set of x86
instruction-set extensions that logically follows SSE4. AVX
increases the width of the 16 XMM registers from 128 bits
to 256 bits; the wider registers have the tasty moniker
YMM. Each register can hold eight single-precision (SP)
floating-point values or four double-precision (DP) floating-
point values that can be operated on in parallel using
SIMD (single-instruction, multiple-data) instructions.
AVX also adds three-register instructions (e.g., c=a+b),
whereas previous instructions could only use two registers
(a=a+b).
Register Files Get Physical
To produce the Sandy Bridge CPU in just two years, Intel’s
Haifa (Israel) team borrowed heavily from the Nehalem
CPU design, following the principle of “if it ain’t broke,
don’t fix it.” Implementing AVX, however, broke the register-
renaming method used in Nehalem (and its predecessor,
Merom, which was also designed by the Haifa team).
In these previous CPUs, each instruction stores its source
values in the scheduler and its result in the reorder buffer
(ROB), which copies the result to the physical register file
once the instruction is retired. In-flight instructions must
check the ROB (using a content-addressable memory) to
locate the most recent copy of any source registers that
they require.
Ring Around the Cores
Sandy Bridge contains a new component, the system agent,
that controls what was previously called the north bridge:
the memory controller, PCI Express, display interfaces,
and the DMI connection to the external south-bridge chip
(PCH). The exact system interfaces will vary depending on
the target platform, but the initial products will support
two DDR3 SDRAM channels and a single ×16 PCI Express
2.0 interface that can also be configured as two ×8 ports.
The chip uses the Embedded DisplayPort interface to connect
to the internal display in a notebook computer. Other
display and system interfaces are in the south bridge.