29-03-2014, 10:36 AM
Seminar Embedded System Objective VHDL
Embedded System Objective.pdf (Size: 248.69 KB / Downloads: 67)
Abstraction
Object Oriented Paradigm (OOP) has changed the perspective how the program must be
written. OOP gives better develop, maintain, analysis, coding, and understanding of complex
system. It affects also VHDL as a language to describe behaviour of digital circuit in field
programmable gate arrays (FPGA) and application specific integration circuit (ASIC). There
are many proposals for extension of VHDL to provide OOP way. One of them is Objective
VHDL. Objective VHDL is designed to fulfil object orientation in VHDL without worrying
about the programming languages will be used in software parts. Objective VHDL has
complete solution from generating high level VHDL until synthesis and simulator.
Introduction
What is VHDL
VHDL (VHSIC Hardware Description Language) is usually used to describe behaviour of
field programmable gate arrays (FPGA) and application specific integration circuits (ASIC) in
electronic design automation of digital circuit. VHSIC is Very High Speed Integrated Circuit.
VHDL is originally developed in US Department of Defense to describe the behaviour of the
ASICs which supplier companies were including in equipment. It simplified to understand all
implementation specific details
The initial version of VHDL, designed to IEEE (Institute of Electrical and Electronics
Engineers) standard 1076-1987, included a wide range data types, such as numerical (integer
and real), logical (boolean and bit), character and time, bit_vector (arrays of bit), and string
(arrays of character). The new IEEE standard 1164 was including multi valued logic which
represented a signal’s drive strength (none, weak, or strong) including unknown values. The
latest version is VHDL 2005.
What is Object Oriented Programming
Object Oriented Programming (OOP) is a computer programming paradigm. The idea of
this paradigm is to implement the functions and instruction in objects or individual units. Each
object can communicated to each other by sending and receiving messages and it looks like
independent unit with it own role.
This paradigm comes up to improve programming languages. The procedural language is
hard to read and understand especially by new programmer or new worker. It makes the
project longer to accomplish.
The advantages are greater flexibility, maintainability, and easy to learn. The power of
OOP approach is often simpler to develop, maintain, analysis, coding, and understanding of
complex situations and procedures than other programming paradigms. It said that OOP is
more real world language because you can see the object but not the structure.
Background of Object Oriented VHDL
Object oriented paradigm attracts many software engineering because it is easy to manage
design complexity and increase software reuse. It affects in VHDL, the object oriented must
include in the standard of VHDL.
The original purpose of VHDL is to describe the behaviour of the system. It encapsulates
the system, more like black box view of piece hardware, and communicates with wire, signal
in term of VHDL. With the same idea behind the making of these models, it is possible to
integrate them.
Development of Object Oriented VHDL
The development of Object Oriented VHDL (OOVHDL) started in the early 1990. Some
researchers make OOVHDL dialects such as VHDL_OBJ [1], VHDL++ [2], and Vista [3] but
the latest news only three still exist. There are Ashenden’s SUAVE [4], Schumacher’s OO-
VHDL [5], and Objective VHDL [6].
The primary target of SUAVE is simulation. Schumacher makes translation from
OOVHDL to VHDL using record and subprograms which lack of VHDL synthesis tools
support. The main emphasize of the Objective VHDL is designed to ease synthesis with some
hardware-related restriction and hardware specific semantics [7].
Summary
Objective VHDL provides object oriented paradigm such as class, object, method,
inheritance, encapsulation, and abstraction. It implements mechanism to deal with object
state, state transition, object lifetime, communication between objects, and request arbitration.
The Objective VHDL supports concurrency. The concurrency is using guard expression
and scheduling policy. There are many implementations of scheduling policy in Objective
VHDL such as static priority, round robin, and enchanted round robin. We can also program
our scheduling policy.
The main advantage and disadvantage of Objective VHDL are the supporting tools. The
tools support ranges are from compiling Objective VHDL source code into the library until
the synthesis of the code and ready to transfer it in hardware level. The tools are also the
limitation of this extension. Because objective VHDL must compatible with the existing
synthesis tools in order to make the code synthesized, it gives to the programmer some
restriction when using this extension.
In the future, we hope for better synthesis tools. Like happened in standard VHDL, the
limitations are arisen from the synthesis side.