25-05-2012, 11:48 AM
Serial-GMII Specification
Serial-GMII Specification.pdf (Size: 80.06 KB / Downloads: 337)
Overview
SGMII uses two data signals and two clock signals to convey frame data and link rate
information between a 10/100/1000 PHY and an Ethernet MAC. The data signals operate at
1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of
operation, each of these signals is realized as a differential pair thus providing signal integrity
while minimizing system noise.
Implementation Specification
This section discusses how this SGMII interface shall be implemented by incorporating and
modifying the PCS layer of the IEEE Specification 802.3z.
Signal Mapping at the PHY side
Figure 2 shows the PHY functional block diagram. It illustrates how the PCS layer shall be
modified and incorporated at the PHY side in the SGMII interface.
Control Information Exchanged Between Links
As described in Overview, it is necessary for the PHY to pass control information to the MAC
to notify the change of the link status. SGMII interface uses Auto-Negotiation block to pass the
control information via tx_config_Reg[15:0].
If the PHY detects the control information change, it starts its Auto-Negotiation process,
switching its Transmit block from “data” to “configuration” state and sending out the updated
control information via tx_config_Reg[15:0]. The Receive block in the MAC receives and
decodes control information, and starts the MAC’s Auto-Negotiation process. The Transmit
block in the MAC acknowledges the update of link status via tx_config_Reg[15:0] with bit 14
asserted, as specified in Table 1. Upon receiving the acknowledgement from the MAC, the
PHY completes the auto-negotiation process and returns to the normal data process.
As specified in Overview, inside the SGMII interface, the Auto-Negotiation link_timer has
been changed from 10 msec to 1.6 msec, ensuring a prompt update of the link status. The
expected latency for the update of link is 3.4 msec (two link_timer time + an acknowledgement
process).
Data Information Transferred Between Links
Below we briefly describe at receive side how GMII signals get transferred across from the
PHY and recovered at the MAC by using the 8B/10B transmission code. The same method
applies to the transmit side.
According to the assertion and deassertion of RX_DV, the PHY encodes the Start_of_Packet
delimiter (SPD /S/) and the End_Of_Packet delimiter (EPD) to signal the beginning and end of
each packet. The MAC recovers RX_DV signal by detecting these two delimiters.
The PHY encodes the Error_Propagation(/V/) ordered_set to indicate a data transmission error.
The MAC asserts RX_ER signal whenever it detects this ordered_set.
CRS is not directly encoded and passed to the MAC. To regenerate CRS, the MAC shall uses
signal RX_DV before it is being passed to the MAC Receive Rate Adaptation block as shown
in Figure 3.
The MAC decodes ENC_RXD[0:9] to recover RXD[7:0].
Bellow Figure 4 illustrates how the MAC samples data in 100 Mbit/s mode. As signals shown
in Figure 2, the GMII data in 100 Mbit/s mode get replicated ten times after passing through
the PHY Receive Rate Adaptation to generate RXD[7:0]. The modified PCS Transmit State
Machine encodes RXD[7:0] to create ENC_RXD[0:9]. As noted in the Overview, the SPD(/S/
) only appears once per frame. SAMPLE_EN is a MAC internal signal to enable the MAC
sampling of data starting at the first data segment (/S/) once every ten data segments in 100
Mbit/s mode.
A note to Figure 4: there is no fixed boundary for the data sampling. Also the first byte of
preamble might be only repeated 9/99 instead of 10/100 times due to the algorithm of the
802.3z PCS Transmit State Machine.
LVDS AC/DC Specification
The basis of the LVDS and termination scheme can be found in IEEE1596.3-1996. Some
parameters have been modified to accommodate the 1.25Gb/s requirements. SGMII consists of
the most lenient DC parameters between the general purpose and reduced range LVDS.
Both the data and clock signals are DC balanced; therefore, implementations that meet the AC
parameters but fail to meet the DC parameters may be AC coupled.
Figure 5 shows the DDR circuit at the source of the LVDS. The circuit passes data and clock
with a 90 degree phase difference. The receiver samples data on both edges of the clock.