18-08-2012, 04:50 PM
Fingerprint image enhancement algorithm implemented on an FPGA
Fingerprint image enhancement.pdf (Size: 334.4 KB / Downloads: 32)
Introduction
FPGA stands for “Field Programmable Gate Array”.
As the name suggest, FPGAs are programmable digital
logic chips. This means that it is possible to program
them to do almost any digital function. The high capability
and performance that FPGAs have achieved
in the last years, allow them to accelerate DSP tasks.
FPGA devices have been used to implement custom
DSPs since the beginning of this decade. The FPGA
devices have benefited from the improvements in VLSI
technology, leading to higher speed and capability as
well as low power consumption. These characteristics,
added to their reprogram ability, make FPGA the most
suitable devices for prototyping and test circuits. They
are flexible and powerful devises and that is why we
choose them to design the circuit for this research.
Fixed point arithmetic
Let us explain about fractional numbers representation
in digital devices, for instance, a computer or,
in our case, the logic circuit in the FPGA. There are
two possible methods, Fixed point and Floating point
representations. The main difference between them is
that, floating point representation can support a much
wider range of values with the same bit word width
than the fixed point representation. The radix point
actually floats, this is, it can be placed anywhere in the
bit word. It is somewhat similar to scientific notation.
The inconvenience with this representation is that it
is more expensive in hardware than fixed point representation
because operations require more complex
hardware.
Circuit design
The system was designed under a general bit word
length of 32 bits, the radix point aligned at the position
16. The pair of the word length and the position of the
radix point is denoted by [32,16]. We will use this notation
from now on. Nevertheless, the word length and
the position of the radix point vary in some regions of
the system, depending on the performing calculation.
This is because during the calculation the range of the
possible values varies dramatically. Hence, in order to
maximize the resource reduction and optimize the precision
of the calculations, it is necessary to adjust the
word length and the position of the radix point.
Hardware implementation
The fingerprint image enhacement algorithm is implemented
on an FPGA device, Xilinx XC3SD1800A
mounted on a Spartan 3A development board. The
resourses available with the FPGA are 16640 slices,
33280 Flip-flops, 33280 4 input LUTs, 84 BRAMs each
of 64 KB and 84 DSP48s. The DSP48 features special
circuits to perform digital signal processing tasks. The
maximum operation frequency is 100 MHz. The software
experiments were done using Matlab. The hardware
experiments for the FPGA simulations were done
using Xilinx System Generator with Simulink and the
FPGA development tool ISE 10.1.
Square root
The development tool ISE provides several libraries to
perform square root, CORDIC, Bipartite tables, Look
up table and Newton-Raphson algorithm. As described
in the previous section CORDIC algorithm was chosen
for the operation. Bipartite tables and Look up table
require a lot of memory resources, and for this application
it is best to save that memory space for image
storage. Newton-Raphson algorithm requires several
multiplier circuits, so it is more expensive in the overall
logic gates count.
System synchronization
An important issue with the system is the synchronization
of the subsystems all together. If the system
is not well synchronized, several processing errors may
occur and result in inaccurate values. To avoid this,
some strategies were applied to the design. Firstly, all
the inputs and outputs of subsystems are registered.
Secondly, the moment when each register is loaded is
triggered by ”Ready” signal provided by the previous
subsystems that generate the data with which the register
is to be loaded. Thirdly, in order to precisely load
this registers and reset the ROM’s address driver, a
special circuit was designed as shown in Fig.6. The
function of this circuit is that once the input changes
from 0 to 1, it sends a pulse with a duration of 1 clock
cycle; this allows to load and reset the necessary elements
at the exact instant.