02-05-2012, 10:50 AM
Seven Level Modified Cascaded Inverter for Induction Motor
Drive Applications
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Introduction
Numerous industrial applications have begun to require higher power apparatus in recent years. Some medium
voltage motor drives and utility applications require medium voltage and MW power level. Therefore high
power and medium voltage inverter has recently become a research focus. As far as conventional two level
inverter is concerned, it exhibits many problems when used in high power applications (Franquelo 2008).
Multilevel inverters have been gained more attention for high power application in recent years which can
operate at high switching frequencies while producing lower order harmonic components.
Cascaded Multilevel Inverter (CMLI)
The general structure of cascaded multilevel inverter for a single phase system is shown in Figure 1. Each
separate voltage source Vdc1, Vdc2, Vdc3 is connected in cascade with other sources via a special H-bridge circuit
associated with it. Each H-bridge circuit consists of four active switching elements that can make the output
voltage either positive or negative polarity; or it can also be simply zero volts which depends on the switching
condition of switches in the circuit. This multilevel inverter topology employs three voltage sources of equal
magnitudes. It is fairly easy to generalize the number of distinct levels (Corzine et al. 2003 and 2004).
Modified Cascaded Multilevel Inverter (MCMLI)
The general structure of a proposed cascaded multilevel inverter is shown in Figure 3. This inverter consists of a
multi conversion cell and an H bridge. A multi conversion cell consists of three separate voltage sources (Vdc1,
Vdc2, Vdc3), each source connected in cascade with other sources via a circuit consists of one active switching
element and one diode that can make the output voltage source only in positive polarity with several levels.
Only one H-bridge is connected with multi conversion cell to acquire both positive and negative polarity. By
turning on controlled switches S1 (S2 and S3 turn off) the output voltage +1Vdc (first level) is obtained.
Similarly turning on of switches S1, S2 (S3 turn off) +2Vdc (second level) output is produced across the load.
Similarly +3Vdc levels can be achieved by turning on S1, S2, S3 switches as shown in Table 1.
PWM for Harmonics Reduction
PWM technique is extensively used for eliminating harmful low-order harmonics in inverters. In PWM control,
the inverter switches are turned ON and OFF several times during a half cycle and output voltage is controlled
by varying the pulse width. SPWM techniques are characterized by constant amplitude pulses with different
duty cycle for each period. The width of this pulses are modulated to obtain inverter output voltage control and
to reduce its harmonic content. Sinusoidal pulse width modulation is the mostly used method in motor control
and inverter application (Ismail 2006).In order to verify the ability of the proposed multilevel inverter topology
to synthesize an output voltage with desired amplitude and better harmonic spectrum, programmed SPWM
technique is applied to determine the required switching angles. It has been proved that in order to control the
fundamental output voltage and eliminate ‘n’ harmonics, ‘n+1’ equations are needed. The method of elimination
will be presented for 7-level inverter such that the solution for three angles is achieved.