18-04-2012, 05:06 PM
Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
CummingsSNUG2002SJ_FIFO2.pdf (Size: 120.8 KB / Downloads: 22)
Introduction
An asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer using
one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain,
where the two clock domains are asynchronous to each other.
One common technique for designing an asynchronous FIFO is to use Gray[4] code pointers that are synchronized
into the opposite clock domain before generating synchronous FIFO full or empty status signals[1]. An interesting
and different approach to FIFO full and empty generation is to do an asynchronous comparison of the pointers and
then asynchronously set the full or empty status bits[6].
This paper discusses the FIFO design style with asynchronous pointer comparison and asynchronous full and empty
generation. Important details relating to this style of asynchronous FIFO design are included. The FIFO style
implemented in this paper uses efficient Gray code counters, whose implementation is described in the next section.
Gray code counter - style #2
One Gray code counter style uses a single set of flip-flops as the Gray code register with accompanying Gray-tobinary
conversion, binary increment, and binary-to-Gray conversion[1].
A second Gray code counter style, the one described in this paper, uses two sets of registers, one a binary counter
and a second to capture a binary-to-Gray converted value. The intent of this Gray code counter style #2 is to utilize
the binary carry structure, simplify the Gray-to-binary conversion; reduce combinational logic, and increase the
upper frequency limit of the Gray code counter.
The binary counter conditionally increments the binary value, which is passed to both the inputs of the binary
counter as the next-binary-count value, and is also passed to the simple binary-to-Gray conversion logic, consisting
of one 2-input XOR gate per bit position. The converted binary value is the next Gray-count value and drives the
Gray code register inputs.
Full & empty detection
As with any FIFO design, correct implementation of full and empty is the most difficult part of the design.
There are two problems with the generation of full and empty:
First, both full and empty are indicated by the fact that the read and write pointers are identical. Therefore,
something else has to distinguish between full and empty. One known solution to this problem appends an extra bit
to both pointers and then compares the extra bit for equality (for FIFO empty) or inequality (for FIFO full), along
with equality of the other read and write pointer bits[1].
Another solution, the one described in this paper, divides the address space into four quadrants and decodes the two
MSBs of the two counters to determine whether the FIFO was going full or going empty at the time the two pointers
became equal.
Conclusion
This paper describes an efficient technique to implement a high-speed asynchronous FIFO, using dual-port RAMs
addressed by Gray counters This design uses an asynchronous comparator for detecting full and empty status.
The technique described implements an asynchronous assertion of the full and empty flags that requires more effort
to analyze for static timing verification.
The technique described also does not have registered full and empty status flags, so care must be taken to insure
that the generation of these flags meets the required timing to recognize assertion of full and empty in the rest of the
system.
This efficient and interesting approach to FIFO design worthy of consideration.