14-09-2013, 03:13 PM
Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL
Aim:
1. Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural
modeling style in Verilog using a Test bench.
2. Synthesize each one of them on two different EDA tools.
Apparatus required:
i) Electronics Design Automation Tools used:
ii)Xilinx Spartan 3E FPGA +CPLD Board
Model Sim simulation tool or Xilinx ISE Simulator tool
iii) Xilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool
iv) Xilinx Project Navigator 13.2 (Includes all the steps in the design flow
fromSimulation to Implementation to download onto FPGA).
v) JTAG cable
vi) Adator 5v/4A