02-05-2013, 02:24 PM
Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
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Abstract
This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.
Introduction
However, the success of VHDL for designing integrated
circuits is indisputable. Unfortunately there is a lack of
tools available linking VHDL tools with such high-level
digital filter design/simulation tools like MatlabTM and
SimulinkTM, which operate on the levels higher than the
structure. At the moment the designer who designed and
tested his design theoretically using high-level tools is
required to spend the same or more time on designing the
structure and the architecture for his theoretical design,
simulate it, test it and fabricate it. This involves a dangerous
break in the integrity of design flow, giving chances for
inconsistencies to creep in. An automated high-integrity
link between theoretical design and implementation is
essential and can be achieved with VHDL via a conversion
tool. A very attractive high-level design/simulation tool is
provided by MathWorksTM and is called SimulinkTM. It is a
very flexible design tool, which allows testing of a highlevel
structural description of the design and makes possible
quick changes and corrections. The circuit description
structure is very similar to the way the design could be
implemented later. Therefore mapping tool allowing
conversion of such a structure into VHDL code would save
the designer’s time, which otherwise has to be spent in
rewriting the same structure in VHDL and probably making
mistakes that will need debugging.
Basics of VHDL
VHDL stands for Very High Speed Integrated Circuits
(VHSIC) Hardware Description Language (HDL). It is a
language for describing digital electronic systems. It was
born out of the United States Government’s VHSIC
program in 1980 and was adopted as a standard for
describing the structure and function of Integrated Circuits
(IC). Soon after it was developed and adopted as a standard
by the Institute of Electrical and Electronic Engineers
(IEEE) in the US (IEEE-1076-1987) and in other countries
[1,2]. VHDL continues to evolve. Although new standards
have been prepared (VHDL-93) most commercial VHDL
tools use 1076-1987 version of VHDL, thus making it the
most compatible when using different compilation tools.
The 1076-1987 standard has also been used here.
VHDL enables the designer to:
· Describe the design in its structure, to specify how it is
decomposed into sub-designs, and how these subdesigns
are interconnected.
· Specify the function of designs using a familiar, C-like
programming language form.
· Simulate the design before sending it off for fabrication,
so that the designer has a chance to rapidly compare
alternative approach and test for correctness without the
delay and expense of multiple prototyping.
Effective Implementation via Simulinkto-
VHDL Conversion Tool.
So far the biggest problem which the designer faces very
often is how to pass from the algorithmic design to its
physical implementation. The first tool the designer uses
when developing the new idea is a high-level design and
simulation tool. One of the most commonly used high-level
tools is MatlabTM with SimulinkTM. It allows the designer to
put together a behavioural or structural simulation very
easily and quickly checking the algorithm or making the
necessary adjustments to it. Working directly with any lowlevel
implementation tool from the start is simply not
practical, as every small change in the algorithm may
sometimes require substantial redesign of the
implementation. Therefore an automatic link between the
high-level algorithmic design, like SimulinkTM model, to
some implementation description, like a target netlist or
VHDL, would lead to great effort and time savings in the
design cycle.
Structural Analysis of the Simulink
Model Description.
As it was pointed out earlier, the description of the
SimulinkTM model has close resemblance to the MatlabTM
structure definition. Describing the model with the structure
would allow simplifying the conversion process as interdependence
of blocks could be indicated by their position in
the tree of blocks. Therefore the conversion of the
MDL-file into the MatlabTM structure was the first task to be
done by the conversion utility developed.
The main problems faced in this stage were:
· The structure obviously can not allow the same field
names at the same level, which was allowed in the
MDL-file. All the blocks and lines (connection signals)
had to be renamed consecutively as a remedy to this
problem. Alternatively they can be combined into a
vector.
· There are no commas to separate parameters and values
in the MDL-file, required by the structure syntax. They
had to be included appropriately.
· There is an inconsistency in the description of text
constants. In MatlabTM they are indicated by a single
quote, in the MDL-file by the double quote. Therefore
single quotes were replaced by double quotes wherever
the text constant was found.
The Basics of the Polyphase IIR
Half-Band Lowpass Filter Structure
The idea of converting the SimulinkTM design into
VHDL has been tested on the example of the two-path twocoefficient
polyphase filter [5,6].
The basic recursive (IIR) allpass filter, shown in
Figure 1(a) is the core of the polyphase IIR structure. For
the case of the half-band lowpass filter two of such allpass
blocks have to be used in a two-path configuration shown in
Figure 1(b), with the appropriate delay in one of the
branches. The higher order filters can be obtained by
cascading a number of basic allpass filters in each path of
the polyphase structure, taking care only to keep the number
of them similar in both paths. By carefully designing the
coefficients, the structure allows to obtain a very highperformance
and relatively easily implementable half-band
lowpass filter.
Conversion of the Model to VHDL
The conversion of the MDL model into VHDL has been
done with the preliminary version of the custom MatlabTM
program. Because of the difficulties in the analysis of the
SimulinkTM description the resulting VHDL code required
some additional editing. The basic blocks like D-type flipflops
with reset, standard logic gates and the two-phase
clock have been designed manually in behavioural
description as part of the library of standard blocks.
A separate test bench has been written. Its purpose was
to compare the results of the VHDL simulation with the
output from the fixed-point SimulinkTM model. The
complete output of SimulinkTM run has been stored in the
file comprising all bits of the input and the output. This file
has been read sample-by-sample and compared with the
output of the VHDL simulation at each clock cycle. The
compilation and simulation of the VHDL code, and
subsequently its synthesis, has been done with PeakFPGA
from Accolade Design Automation Inc. [3] provided by the
company for the purpose of evaluation.
Conclusions
The example design of the polyphase filter and then its
conversion into VHDL proved that such an idea would be a
very attractive way of designing test chips very quickly. It
took three days to get from the SimulinkTM model to its final
synthesised version. The next stage of the research work
would be either to compile to a custom layout and put it
onto silicon or to commit the design onto a standard FPGA.
The current version of the program performs only direct
mapping of structures from SimulinkTM to VHDL and does
not work for multiplexed architectures. In order to do such
conversion the program requires an algorithm analysing
behavioural or structural descriptions to find common
operators, and convert them into the multiplexed structure
with added control circuitry. This will be the aim of the
future work.