06-12-2012, 12:00 PM
A Compact and Efficient FPGA Implementation of the DES Algorithm
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Abstract.
In this paper we present an efficient and compact reconfigurable
hardware implementation of the Data Encryption Standard
(DES) algorithm. Our design was implemented on a VirtexE XCV400e
device. As a strategy to reduce the associated design critical path, we
utilized a parallel structure that allowed us to compute all the eight
DES S-boxes simultaneously. Our DES round design achieved a data
encryption/decryption rate of 274 Mbits/s occupying only 117 CLB
slices. These results are quite competitive when compared with other
reported reconfigurable hardware implementations of DES.
Introduction
Cryptography is the main mechanism to secure digital information data. In
recent years due to the heavy increase in the volume of information data, secure
and rapid cryptographic algorithms were developed to combat security
threats and security measures were considered to be essential wherever, digital
data transactions have to be performed. The elevated diversity seen on security
applications posed an additional challenge since highly secure algorithms were
not the only requirement but rather high performance for some applications
and for others, less space. In that scenario, cryptographic designers have explored
not only realizations on software platforms, but also on classic hardware
or reconfigurable hardware platforms as well.
The DES Algorithm
On August, 1974, IBM submitted a candidate (under the name LUCIFER) for
cryptographic algorithm in response to the second call from National Bureau
of Standards (NBS), now the National Institute of Standards & Technology
(NIST)[15], to protect data during transmission and storage. NBS launched
an evaluation process with the help of National Security Agency (NSA) and
finally adopted on July 1977 a modification of LUCIFER algorithm as the new
Data Encryption Standard (DES). The Data Encryption Standard [16], known
as Data Encryption Algorithm (DEA) by the ANSI [17] and the DEA-1 by the
ISO [18] remained a worldwide standard for a long time and was replaced by
the new Advanced Encryption Standard (AES) on October 2000. However, it
is expected that DES will remain in the public domain for a number of years.
A Reconfigurable Hardware DES Implementation
Referring to Fig. 1, the 16 iterations of the identical operations are repeated
which come under the name of a function f (R,K). DES combines first permutation,
function f (R,K), second permutation, and key schedule for one encryption
as shown in Fig. 2. As it was mentioned before, DES encryption and decryption
routines are the same. Only the order of the sub-keys is reversed in case
of decryption.
Implementation summary
FPGA implementation of DES algorithm was accomplished on a VirtexE device
XCV400e-8-bg560 using Xilinx Foundation Series F4.1i as synthesis tool.
The design was coded using VHDL language. It occupied 165 (3%) CLB slices,
117 (1%) slice Flip Flops and 129 (41%) I/Os. The design achieves a frequency
of 68.05 MHz (14.7 ηS). It takes 16 clock cycles to encrypt one data block
(64-bits). Therefore, the achieved throughput is (68.05×64)/16=274Mbits/s.
4 Performance comparison
Table 1 shows the performance figures for some representative DES hardware
implementations. Notice that the achieved results are competitive with the
existing implementations.
Conclusions
In this work, an efficient and compact DES implementation on reconfigurable
hardware platforms was presented. VLSI or FPGA implementations achieve
ultra high throughputs depending on the design strategy; design resources and
optimization work both at algorithm and design level. From Table 1, it can be
seen that our design achieved a competitive performance when compared with
other reported reconfigurable hardware implementations of DES.
Our architecture can be improved to offer even better results in terms of
achieved throughput. The most obvious extension is to design a fully pipelined
architecture in order to obtain a higher throughput at the price of area.