13-08-2012, 03:42 PM
Speed Comparison of 16x16 Vedic Multipliers
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ABSTRACT
The paper presents the concepts behind the "Urdhva
Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication
techniques. It then shows the architecture for a 16×16 Vedic
multiplier module using Urdhva Tiryagbhyam Sutra. The paper
then extends multiplication to 16×16 Vedic multiplier using
"Nikhilam Sutra" technique. The 16×16 Vedic multiplier
module using Urdhva Tiryagbhyam Sutra uses four 8×8 Vedic
multiplier modules; one 16 bit carry save adders, and two 17 bit
full adder stages. The carry save adder in the multiplier
architecture increases the speed of addition of partial products.
The 16×16 Vedic multiplier is coded in VHDL, synthesized and
simulated using Xilinx ISE 10.1 software. This multiplier is
implemented on Spartan 2 FPGA device XC2S30-5pq208. The
performance evaluation results in terms of speed and device
utilization are compared with earlier multiplier architecture. The
proposed design has speed improvements as compared to
multiplier architecture presented in [5].
INTRODUCTION
Vedic mathematics was rediscovered in the early twentieth
century from ancient Indian sculptures (Vedas). Ancient Indian
system of mathematics was derived from Vedic Sutras. The
conventional mathematical algorithms can be simplified and
even optimized by the use of Vedic mathematics. The Vedic
algorithms can be applied to arithmetic, trigonometry, plain and
spherical geometry, calculus.
In [1], authors have proposed a new multiplier based on an
Vedic algorithm for low power and high speed applications.
Their multiplier architecture is based on generating all partial
products and their sums in one step. They claim that their
proposed Vedic multiplier is faster than the corresponding array
multiplier and Booth multiplier. The authors in [2] have tested
and compared various multiplier implementations such as Array
multiplier, Multiplier macro, Vedic multiplier with full
partitioning, Vedic multiplier using 4 bit macro, fully Recursive
Vedic multiplier, Vedic multiplier using 8 bit macro for
optimum speed. They have claimed that Vedic method is not
fundamentally different from conventional method of
multiplication.
Vedic Multiplier using ‘Urdhva
Tiryagbhyam’Sutra
The „Urdhva Tiryagbhyam‟ Sutra [5-10] is a general
multiplication formula applicable to all cases of multiplication.
„Urdhva‟ and „Tiryagbhyam‟ words are derived from Sanskrit
literature. „Urdhva‟ means “Vertically” and „Tiryagbhyam‟
means “crosswise”.
The multiplication of two 2-digit decimal numbers 21 and 32 is
shown in Figure 1. The least significant digit 1 of multiplicand is
multiplied vertically by least significant digit 2 of the multiplier,
get their product 2 and set it down as the least significant part of
the answer. Then 2 and 2, 1 and 3 are multiplied crosswise, add
the two, get 7 as the sum and set it down as the middle part of
the answer. Then 2 and 3 is multiplied vertically, get 6 as their
product and put it down as the last the left hand most part of the
answer.
RESULTS AND DISCUSSION
Table-1 displays the comparison of synthesis results of the
proposed 16x16 Vedic multiplier using Nikhilam Sutra with
16x16 Vedic multiplier using Urdhva Tiryagbhyam Sutra
presented in [5].
It has been observed that for 16x16 Vedic multiplier module
using Nikhilam Sutra , the gate delay is 33.729 ns with Device
utilization (number of slices- 45%) while it is 41.751 ns with
Device utilization (number of slices- 87%) for the 16x16 Vedic
multiplier module using Urdhva Tiryakbhyam Sutra.
CONCLUSION
The proposed Vedic multiplier architecture shows speed
improvements over multiplier architecture presented in [5]. The
16x16 Vedic multiplier using „Nikhilam‟ Sutra found to be
better than 16x16 Vedic multiplier using „Urdhva Tiryakbhyam‟
Sutra in terms of speed when magnitude of both operands are
more than half of their maximum values . This approach may be
well suited for multiplication of numbers with more than 16 bit
size.