09-04-2012, 04:20 PM
VLSI Implementation of an Edge-Oriented Image Scaling Processor
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INTRODUCTION
I MAGE scaling is widely used in many fields [1]–[4],
ranging from consumer electronics to medical imaging.
It is indispensable when the resolution of an image generated
by a source device is different from the screen resolution of a
target display. For example, we have to enlarge images to fit
HDTV or to scale them down to fit the mini-size portable LCD
panel. The most simple and widely used scaling methods are
the nearest neighbor [5] and bilinear [6] techniques. In recent
years, many efficient scaling methods have been proposed in
the literature [7]–[14].
AREA-PIXEL SCALING TECHNIQUE
In this section, we first introduce the concepts of the areapixel
scaling technique. Then the hardware implementation issues
of it are briefly reviewed.
A. An Overview of Area-Pixel Scaling Technique
Assume that the source image represents the original
image to be scaled up/down and target image represents the
scaled image. The area-pixel scaling technique performs
scale-up/scale-down transformation by using the area pixel
model instead of the common point model. Each pixel is treated
as one small rectangle but not a point; its intensity is evenly
distributed in the rectangle area.
VLSI ARCHITECTURE
Our scaling method requires low computational complexity
and only one line memory buffer, so it is suitable for low-cost
VLSI implementation. Fig. 9 shows block diagram of the sevenstage
VLSI architecture for our scaling method. The architecture
consists of seven main blocks: approximate module (AM), register
bank (RB), area generator (AG), edge catcher (EC), area
tuner (AT), target generator (TG), and the controller. Each of
them is described briefly in the following subsections.
SIMULATION RESULTS AND CHIP IMPLEMENTATION
To evaluate the performance of our image-scaling algorithm,
we use 12 gray-scale test images of 512 512 8 b, shown in
Fig. 15. For each single test image, we reduce/enlarge the original
image by using the well-known bilinear method, and then
employ various approaches to scale up/down the bilinear-scaled
image back to the size of the original test image. Thus, we
can compare the image quality of the reconstructed images for
various scaling methods.
CONCLUSION
A low-cost image scaling processor is proposed in this paper.
The experimental results demonstrate that our design achieves
better performances in both objective and subjective image
quality than other low-complexity scaling methods. Furthermore,
an efficient VLSI architecture for the proposed method is
presented. In our simulation, it operates with a clock period of
5 ns and achieves a processing rate of 200 megapixels/second.
The architecture works with monochromatic images, but it can
be extended for working with RGB color images easily.