04-11-2016, 09:28 AM
1464276517-sincypaper.doc (Size: 822 KB / Downloads: 6)
Abstract: The usage of Bulk FinFETs have gained interest due to its low wafer cost, less defect density and less heat transfer but the problem of substrate leakage is present. Substrate doping and variation in isolation oxide thickness are the methods to reduce off current. Technology complexity and mobility degradations prevent the usage of this method. Stack gate technology reduces leakage by using two gate materials with undoped substrate. This method is free from random dopant fluctuations.
Keywords: Bulk FinFET, substrate doping, stack gate FinFET, Threshold voltage, DIBL.
Introduction
In the emerging technologies, non-planar transistors such as double-gate FinFETs and tri-gate transistors are now being manufactured [1-3]. Since there is reduction of short-channel effect in the multigate transistors, Moores law is still satisfied from conventional device scaling without using new material for substrate. Even though new devices are manufactured on SOI wafers, FinFETs on bulk substrate is also in demand. They have less defect density, cooler and are cheaper due to bulk body and mass production.
Substrate leakage is the main disadvantage of bulk FinFET [4-7]. It is due to the presence of extra carriers in the bulk. This disadvantage can be overcome by implementing the methods like
substrate doping and the variation in the isolation oxide thickness. But these remedies result in the problems like the increase in technology complexity, mobility degradation and reduction in the effective fin height [8]. A new approach has to be developed to remove these problems.
The paper introduces a new structure with two gate materials. The bottom gate material is having higher work function and top gate material is having lower work function. The analysis of the relationship between thickness, work function and the off current is discussed in the coming sections. The simulations are carried out in 3D Cogenda TCAD device simulator.
Conventional Bulk FinFET
Device Structure
The conventional bulk FinFET in 3-D and 2-D view are respectively shown in Figure 1 a) and b). The simulations are based on 11.9nm technology [9] node in ITRS and the table 1 shows the list of specifications and corresponding values used for bulk FinFET.
Uniform doping profile is assumed in the source/drain extension (SDE), and Gaussian doping profile is in bulk-Si substrate for punch through stopping (PTS). Also the channel (or the fin) could be partially doped to prevent the bottom-up diffusion of the PTS doping. The simulations are carried out with Fermi-Dirac statistics, drift-diffusion transport using Philips unified model and the density gradient quantization model.
Leakage suppression methods
While using bulk FinFET [8], excess carriers under the fin or channel will increase the substrate leakage. Previous works shows that leakage current can be suppressed by using additional steps like substrate doping and isolation oxide thickness increment.
Figure 2 shows the drain current (IDS) versus gate voltage (VGS) for bulk FinFET with and without substrate doping. Also it is investigated that doping depth increment will reduce the substrate leakage further because of the recombination of excess carriers in the substrate. Tdoping=distance for the graded doping profile from top of the substrate to downwards
Proposed Stack Gate Structure
A new structure with two gate materials for bulk FinFET[12] is presented here. Previous discussions shows that extra carriers in the substrate are the main cause of substrate leakage. So the aim is to find an alternative way to suppress off current. Figure 7 a) shows the proposed stack gate bulk structure where we use top gate material as n-type polysilicon for n-FinFET and bottom gate as p-type polysilicon or metal FinFET and b) shows structure drawn in device simulator. Using this structure, the substrate region close to the fin can be in a near-accumulation condition simply by adjusting gate work function of the bottom gate. The stack gate is advantageous in leakage current suppression because the p-type-doped (NPolySi = 1019 cm-3) or equivalent metal (work-function = 5.29eV) bottom gate lowers the electron density due to improved electric field control over the lower fin region.
Conclusion
The stack gate technique is an easiest method for leakage suppression. Leakage suppression is obtained by varying the thickness of bottom gate and also by varying the work-function of the bottom gate electrode.
A stack gate structure was proposed to suppress leakage current effectively without extra doping and without compromising the effective fin height. The proposed technique is compatible with CMOS applications when using gate-last high-k metal gate process. Both poly- silicon and metal gates were shown to be feasible in the proposed stack gate. Furthermore, IOFF is comparable with the case on SOI substrate. By properly choosing the work function of bottom gate, IOFF can be even lower than that of the SOI counterpart. Since PTS doping is not needed in random dopant fluctuations is obtained.