03-01-2013, 03:53 PM
Study and Parametric Analysis of Tunnel FET for Digital/Analog VLSI Circuits
Study and Parametric.pdf (Size: 376.96 KB / Downloads: 54)
Introduction
Aggressive scaling of MOSFETs beyond sub-100nm length and
near sub-threshold voltage to meet various design constraints like
power, area, functions etc imposed some serious bottelnecks.
Increase of short channel and high field effects
Drain induced barrier lowering (DIBL)
Gate induced drain leakage (GIDL)
Vth roll-off
Fowler-Nordheim and direct tunneling through the gate oxide
Statistical distribution of doping atoms in the channel
Above points are related to the physical nature of device. Hence, a
detailed analysis at device level is required to address these issues
Tunnel FETs are considered as one of the best alternative for
conventional MOSFETs due to their low leakage currents, less
susceptibility to short channel effects (SCEs) and feasibility of
integration with standard CMOS process flow
For most the above discussed novel methods ION , ION/IOFF ,
Subthreshold Swing,Ambipolar Nature have not been
addressed simultaneously.
For most the device architectures AC and DC parameter
analysis are yet to done so as to go for the best optimized
design.
Compact modeling of these devices are still far to complicated
and not been accomplished so far sucessfully.
Circuit and Device co-optimization has not been addressed
properly.