29-09-2012, 12:09 PM
Sub-System Design 1
Sub-System Design 1.ppt (Size: 30.5 KB / Downloads: 108)
Introduction
Large systems are composed of sub-systems, known as Leaf-Cells
The most basic leaf cell is the common logic gate (inverter, nand, ..etc)
Structured Design
High regularity
Leaf cells replicated many times and interconnected to form the system
Logical and systematic approach to VLSI design is essential
Good Design Methodology
Define Requirements
Partition overall architecture into appropriate sub-systems
Consider communication paths in order to develop sensible interrelationships between subsystems
Draw a floor-plan of how the system is to map onto silicon and iterate above as appropriate
Aim for regular structures so that design is largely a matter of replication
Lay-out each cell (stick diagram)
Carry out design rule checks
Simulate performance of each cell / subsystem
Computer Aided Design
Early CAD systems used a graphical editor to design the layout of the chip directly - this is now impractical for anything above small scale integration
Designing a chip requires a variety of CAD tools, both the analyze the design and synthesize parts of the design
CAD tools are used at many stages in the design and so must be able to communicate with each other.
Computer aided design approaches make use of cell libraries consisting of tested and debugged transistor circuits
Analysis and design verification tools are required to achieve correct designs before chips are manufactured
Major Levels of Design
Specification
Description of requirements
Systems Level
placing and interconnecting major functional units
Function Level
specification and design of major functional units
Logic/Circuit Level
Gate level design, gate interconnection design
Layout Level
what will actually be patterned onto the chip, how the chip will be processed
Physics Level
the physics of gate and switch operation
Silicon Compilation
Chip design systems have some similarity to language compilation systems
they take in a high level description of a system
they output the device layout (like machine code)
they reuse tried and tested components (like libraries)
Scaling
As fabrication techniques improve, transistors get smaller and smaller
The libraries can be made scale - invarient so that re-engineering for smaller feature size involves only recompilation
Why Integration?
Lower parasitics = higher speed
Lower power consumption
Physically smaller
Higher reliability ( due to reduced interconnections)
Repeatability - Whole systems on single chip
Cost
Integration reduces cost for large volumes
Relatively less manual assembly
Lower cost per unit
Top - Down vs Bottom - Up Design
Top down design adds functional detail - creates lower levels of abstraction from upper levels
Bottom up design creates abstractions from low level behaviour
Good design effort needs both top down and bottom up