14-08-2012, 03:05 PM
Survey on Power Management Techniques for Energy Efficient Computer Systems
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Abstract
In this paper we describe different power management techniques aiming to reduce power
consumption in computer systems. On one hand, static techniques, applied at design time, have
been presented with a variety of simulation and measurement tools, targeting different levels of
the system’s hardware and software components. On the other hand, dynamic power
management techniques, applied at runtime, were also discussed. These dynamic techniques aim
at reducing energy consumption at CPU level, using DVS, but also try to save energy of the
overall system and even on a cluster system level.
Introduction
Performance optimization has long been the goal of different architectural and systems software
studies, driving technological innovations to the limits for getting the most out of every cycle.
This quest for performance has made it possible to incorporate millions of transistors on a very
small die, and to clock these transistors at very high speeds. While these innovations and trends
have helped provide tremendous performance improvements over the years, they have at the same
time created new problems that demand immediate consideration. An important and daunting
problem is the power consumption of hardware components, and the resulting thermal and
reliability concerns that it raises making power as important a criterion for optimization as
performance in both high-end and low-end systems design.
Static Power Management (SPM) Techniques
Power dissipation limits have emerged as a major constraint in the design of microprocessors, and
just as with performance, power optimization requires careful design at several levels of the
system architecture. Different energy models were presented in previous studies and integrated
with already known simulators and measurement tools, targeting different system levels and
providing power estimation, measurement and optimization at design time.
These studies can be divided mainly into two areas. The first one is a low-level approach
targeting the CPU and investigating its power consumption at both cycle and instruction levels.
This CPU-level approach will be described in subsection 2.1. The second approach is a high-level
approach targeting different or all system components. This system-level approach will be
described in subsection 2.2.
CPU-level SPM
Power consumed by the CPU is significant. In papers [1-5], the CPU was the main target of
power consumption analysis. Many power-aware models were presented and integrated into
already-in-use performance simulators in order to investigate power consumption of the CPU, on
a unit basis or for the processor as whole. These investigations were mainly held on two
abstraction levels: the register-transfer level (or cycle-level), described in subsection 2.1.1, and
the instruction-level, in subsection 2.1.2.
Register-transfer level
Processor energy consumption is generally estimated by register-transfer level (RTL) or cyclelevel
simulators [1-3]. During every cycle of the simulated processor operation, the activated (or
busy) microarchitecture-level units or blocks are known from the simulation state. Depending on
the workload, a fraction of the processor units are active at any given cycle. We can use these cycle-by-cycle resource usage statistics, available from a trace or execution-driven performance
simulator, to estimate the unit-level activity factors. If accurate energy models exists for each
modeled resource, on a given cycle and if unit i is accessed or used, we can estimate the
corresponding energy consumed and add it to the net energy spent overall for that unit. So, at the
end of a simulation, we can estimate the total energy spent on a unit basis as well as for the whole
processor.
Instruction-level
An additional approach for energy estimation, using instruction-level power analysis, was
presented in [4,5]. This technique estimates the energy consumed by a program by summing the
energy consumed by the execution of each instruction. Instruction-by-instruction energy costs are
precharacterized once for all for each target processor.
In [4], processor instruction-level simulator and memory model were tightly integrated
together with an accurate battery model. A methodology was developed were each component is
characterized with equivalent capacitance for each of its power states. Energy spent per cycle is a
function of equivalent capacitance, current voltage, and frequency. The equivalent capacitance
allows to easily scaling energy consumed for each component as frequency or voltage of
operation change. Equivalent capacitances are calculated given the information provided in data
sheets. The total energy consumed by the system per cycle is the sum of energies consumed by
the processor and L1 cache, interconnects and pins, memory, L2 cache, the DC-DC converter and
the efficiency losses in the battery. Models for energy consumption and performance estimation
of each of these system components were described in [4]. The system used to illustrate this
methodology is the SmartBadge with an ARM processor. As a result, the energy models were
implemented as extensions to the instruction-level simulator for the ARM processor family called
the ARMmulator normally used for functional and performance validation.
System-level SPM
There is little benefit in optimizing only the CPU core if other elements participate or sometimes
even dominate the energy consumption. To effectively optimize system energy, it is necessary to
consider all of the critical components. Different papers [6-9] investigate the power consumption
on different system levels, targeting both hardware and software on different levels of abstraction.
In subsection 2.2.1, state-level models and measurements are used to account for the
energy consumption of the whole system based on the state each device is in or transiting from or
to. In subsection 2.2.2, measurements are used to find the system power consumption and help
targeting the hotspots in applications and operating system procedures. This approach tries to
reduce energy consumption by acting on the application- and OS-level. Finally, subsection 2.2.3
describes a complete system level simulation tool which models the CPU, memory hierarchy and
a low power disk subsystem and quantifies the power behavior of both the application and
operating system.