22-10-2012, 10:44 AM
B.TECH. ECE- IV YEAR-I SEM E-CAD AND VLSI LAB LIST OF EXPERIMENTS
programs.doc (Size: 295 KB / Downloads: 45)
1. HDL code to realize all the logic gates
1.1. Logic Gates (Data Flow Model)
1.2. Logic Gates (Behavioral Model)
1.3. Nand Logic Gate (Structural Model)
1.4. Nor Logic Gate (Structural Model)
1.5. XNor Logic Gate (Structural Model)
2. Design of 2-to-4 decoder
3. Design of 8-to-3 encoder
3.1. Without priority
4. Design of 8-to-1 multiplexer
5. Design of 4 bit binary to gray converter
6. Design of Demultiplexer & comparator
6.1. Demultiplexer
6.2. 4-bit Comparator
7. Design of full adder using 3 modeling styles
7.1. Full adder (dataflow Model)
7.2. Full adder (Behavioral Model)
7.3. Full adder (Behavioral Model with Select)
7.4. Full adder (Structural Model)
8. Design of flip flops: SR,D,JK,T
8.1. SR flip flop
8.2. D flip flop
8.3. JK flip flop
8.4. T flip flop
9. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset)
9.1. 4-bit synchronous counter
9.2. 4-bit asynchronous counter
9.3. BCD up counter
9.4. BCD down counter
10. Finite state machine design