05-07-2012, 04:00 PM
TESTING VLSI CIRCUITS FROM VHDL DESCRIPTIONS
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Introduction
Because of the increase in VLSI circuits complexity, throughout
the last years, the use of more powerful CAD tools is needed.
Designers have to deal with circuits containing hundreds of
thousands transistors, which may make the design and verification
tasks unaffordable.
First CAD tools appeared twenty years ago, trying the lowest
level work automation, as physical design verification, electrical
and switch level simulation, etc. In a second phase, some tools
working at the logic gate level came out, making the designer’s
work easier, as a consequence of the reduction in the number of
primitives, clearly lower using gates than using transistors and
switches. Nowadays, there may be many thousands of gates
included in a single chip. So, digital designs should be treated from
higher levels of abstraction. New design methodologies are used,
based on top-down approaches. They begin with a behavioral model
of the system and functional simulation, then a register-transfer
level description and its synthesis to obtain the circuit structure.
With the new automatic synthesis tools this task can be easily done.
These tools extract the structure of a digital circuit from a registertransfer
description [ I].
Brief Description of VHDL
VHDL is a language used to describe digital electronic systems,
that was defined by the DoD into its VHSIC (Very High Speed
Integrated Circuits) program. It is well suited for VLSI design, but
not restricted to it. The language was adopted by IEEE and defined
as standard at the end of 1987 [2].
At the beginning, it was conceived just as a description and
simulation language, which could be used to specify digital systems.
Later on, it has been adopted as the basis for other tasks, more
closely related to integrated circuits design, like synthesis. The full
VHDL, defined in the standard, is not synthesizable; in other
words, not all the constructs and statements of the language are
directly related to hardware structures. The result is that synthesis
tools use just a subset of the language, as it is explained in [3].
VHDL handles different levels of abstraction to describe
hardware, from the pure structure to the behavior of a system.
Structural descriptions are similar to hierarchical netlists, including
the component definitions and their interconnections. Behavioral
models are based on algorithm descriptions, similar to those written
in a programming language, like PASCAL or C.
The Behavioral Fault Model
At this point, we will try to establish a new fault model for
behavioral descriptions in VHDL. The fault effect is the
perturbation of the VHDL code. Therefore, faults will change the
data transfers, the control flow and the activation of statements.
The only way to obtain a fault model is by an abstraction process
of the failures of the devices, as it has been already mentioned. So,
we will do it in the same way some other fault models have been
defined. Stuck-at-0 (1) models at the gate level are no more than
abstractions. A further step may be taken going up to the behavioral
level. Anyway, stuck-at model may be used as a reference because
it has been assayed experimentally.
Conclusions
A new approach for solving the test problem of VLSI circuits
has been proposed. A fault model for VHDL descriptions is
developed and their corresponding mappings in the code are
explained. The main advantages of these techniques are that the
results obtained for behavioral descriptions may be useful
independently of the implementation technology chosen, and
additional information is present in behavioral descriptions which
is not in gate level descriptions. A promising research area is
opened with these techniques that may exploit the new synthesis
tools for ASIC design appeared in the last years. The future work
is oriented to find the redundancies in the fault model definition and
to obtain a simple but acceptable and well-contrasted fault model.