24-11-2012, 12:57 PM
Terasic SFP HSMC Board User Manual
Terasic SFP.pdf (Size: 2.14 MB / Downloads: 20)
Introduction
The Small Form-Factor Pluggable (SFP) HSMC board is a hardware platform for evaluating the interoperation
of Altera FPGA, specifically Stratix IV GX, Arria GX, and Arria II GX, with generic SFP modules. The optical
modules that are of particular importance are SGMII Ethernet, Fiber channel, CPRI/OBSAI and SONET.
Furthermore, the SDI HSMC board is intended for customers to implement both telecommunication and data
communications applications.
Power Supply
This section describes the power supply on the SFI HSMC board
The SFP HSMC is powered through the HSMC connector’s 3.3V and 12V pins. The SFP and clocking
circuitry requires 3.3V. A switching regulator powered from the 12 HSMC input produces 4V. Three linear
regulators powered from 4V will produce the 3.3V. The switching frequency is set to 1MHz. The power
distribution network is shown in the figure below. Max power consumption is estimated at 1A on 12V.
Typical power consumption is considerably less than this.
Overview
This section describes the design concepts for the SFP HSMC demonstration.
The demonstration is operating on Stratix GX Development Board HSMC Port B interface testing the four
Transceiver/LVDS channels at 6.25Gbps. The transceiver signals HSMB[0:3] on the Stratix IV GX FPGA
Development board are looped back through the SFP HSMC daughter board. The SFP HSMC board must
have SFP modules inserted in SFP[0:3] locations with a loopback from SFP TX to SFP RX on each module.
Four transceiver channels of pseudo-random data are 8B/10B encoded, serialized, pre-emphasized and
transmitted out according to the following signals HSMB_TX_P/N[3:0] of the Stratix IV GX device at
6.25Gbps. These high-speed serial data are then looped back through an external SFP HSMC back to the
Stratix IV GX device. Through the SFP HSMC board the data is then equalized, retimed, deserialized, word
aligned, 8B/10B decoded, channel bonded, and then the four bonded channels are compared against a
receive side PRBS generator inside the Stratix IV GX FPGA fabric.