14-05-2013, 02:13 PM
The Thumb Instruction Set
The Thumb Instruction.pdf (Size: 153.1 KB / Downloads: 20)
The Thumb Instruction Set
The Thumb instruction set addressed the issue of code density.
It may be viewed as a compressed form of a subset of the ARM instruction
set.
Thumb is not a complete architecture. It only supports common application
functions, allowing recourse to the full ARM instruction set where
necessary.
ARM processors which support the Thumb IS can also execute the
standard 32-bit ARM IS. Not all ARM processors are capable of executing
Thumb instructions.
The Thumb bit in the CPSR
The interpretation of the instruction stream at any particular time is
determined by bit 5 of the CPSR, the T bit (see pp. 40). If T is set the
processor interprets the instruction stream as 16-bit Thumb instructions,
otherwise it interprets it as standard ARM instructions.
Thumb Systems
A typical embedded system will include a small amount of fast 32-bit
memory on the same chip as the ARM core and will execute speed-critical
routines (such as digital signal processing algorithms) in ARM code from
this memory. The bulk of the code will not be speed-critical and may
execute from a 16-bit off-chip ROM.
Thumb-ARM differences
In order to achieve a 16-bit instruction length a number of characteristic
features of the ARM IS have been abandoned:
• Most Thumb instructions are executed unconditionally. (All ARM instructions are executed
conditionally.)
• Many Thumb data processing instructions use a 2-address format. (the destination register is
the same as one of the source registers). (ARM data processing instructions, with the
exception of the 64-bit multiplies, use a 3-address format.)
• Thumb instruction formats are less regular than ARM instruction formats, as a result of the
dense encoding.
Thumb Instruction Mapping
The Thumb decompressor performs a static translation from the 16-bit
Thumb instruction into the equivalent 32-bit ARM instruction. This involves:
• Performing look-up to translate the major and minor opcodes.
• Zero-extending the 3-bit register specifiers to 4-bit specifiers.
• Mapping other fields across as required.