02-05-2013, 03:46 PM
The VHDL Golden Reference Guide
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A Brief Introduction To VHDL
The following paragraphs give a brief technical introduction to
VHDL suitable for the reader with no prior knowledge of the
language. As will be evident from these paragraphs, VHDL uses a lot
a specialised technical jargon!
Background
The letters VHDL stand for the VHSIC (Very High Speed Integrated
Circuit) Hardware Description Language. VHDL is a language for
describing the behaviour and structure of electronic circuits, and is
an IEEE standard (1076).
VHDL is used to simulate the functionality of digital electronic
circuits at levels of abstraction ranging from pure behaviour down to
gate level, and is also used to synthesize (i.e. automatically generate)
gate level descriptions from more abstract (Register Transfer Level)
descriptions. VHDL is commonly used to support the high level
design (or language based design) process, in which an electronic
design is verified by means of thorough simulation at a high level of
abstraction before proceeding to detailed design using automatic
synthesis tools.
VHDL became an IEEE standard in 1987, and this version of the
language has been widely used in the electronics industry and
academia. The standard was revised in 1993 to include a number of
significant improvements.
The Language
In this section as in the rest of the guide, words given in Capitalised
Italics are technical terms whose definitions may be found in the
main body of this guide.
An hierarchical portion of a hardware design is described in VHDL
by an Entity together with an Architecture. The Entity defines the
interface to the block of hardware (i.e. the inputs and outputs), whilst
the Architecture defines its internal structure or behaviour. An Entity
may possess several alternative Architectures.
Hierarchy is defined by means of Components, which are analogous
to chip sockets. A Component is Instantiated within an Architecture to
represent a copy of a lower level hierarchical block. The association
between the Instance of the Component and the lower level Entity and
Architecture is only made when the complete design hierarchy is
assembled before simulation or synthesis (analogous to plugging a
chip into a chip socket on a printed circuit board).
Compilation
VHDL source code is usually typed into a text file on a computer.
That text file is then submitted to a VHDL compiler which builds the
data files necessary for simulation or synthesis. The proper jargon for
the steps performed by the compiler are Analysis, which checks the
VHDL source for errors and puts the VHDL into a Library, and
Elaboration, which links together the Entities and Architectures of the
hierarchy.