30-03-2012, 11:44 AM
Three-dimensional Image Processing VLSI System with Networkon-
chip System and Reconfigurable Memory Architecture
06018893.pdf (Size: 2.82 MB / Downloads: 63)
INTRODUCTION
Recently, image processing technology has been widely
used in vision system, multimedia processor, and consumer
electronics [1]. Rapid developing technology requires high
performance image processor with fast computation speed,
small chip size and low power consumption. In addition,
flexible data flow, robust signal control and inner write/read
operation are also important for image processing system.
II. THREE-DIMENSIONAL LAYER ARCHITECTURE
The three-dimensional (3D) architecture for parallel image
processing system is shown in Fig. 1. Many different function
layers are stacked vertically and the Through-Silicon Via
(TSV) can be used to connect whole chip layers with specific
stacking sequence. By effective function layer design and
precise inter-layer connection, 3D architecture can reduce chip
size, drop power consumption and accelerate system speed. In
addition, image data transmission, system signal bandwidth,
and analog-digital converter efficiency can also be
significantly improved.
3D RAM/ROM SYNTHESIS DESIGN SYSTEM
A. Synchronous System Architecture
The RAM and ROM modules are used together to realize
better data write/read and inner-chip signal control in 3D
image system. New 3D processing technology with Flip-Flop
and clock buffer is proposed to generate input image signals
as in Fig. 2. To enable system control and data pipeline,
synchronous signal system is used in 3D RAM/ROM codesign
system.
CONCLUSION
In this paper, new reconfigurable system with RAM/ROM
memory modules and 3D layer architecture is proposed for
highly pipeline image processing chip. Flexible data flow and
direct system control can be realized by precise data fetch in
RAM and ROM memory.