26-02-2013, 12:53 PM
Traffic Lights
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INTRODUCTION
It is often useful to be able to sequence through an arbitrary number of states,
staying in each state an arbitrary amount of time. For example, consider the set of traffic
lights shown in Figure 8.13. The lights are assumed to be at a four-way intersection with
one street going north-south and the other road going east-west.
To simulate these traffic lights we will use the red, yellow, and green LEDs
connected to ld[7:2] on the BASYS board and cycle through the six states shown in Table
8.2. A state diagram for controlling these traffic lights is shown in Fig. 8.14. If we use a
3 Hz clock to drive this state diagram then a delay of 1 second is achieved by staying in a
state for three clock cycles. Similarly, a delay of 5 second is achieved by staying in a
state for fifteen clock cycles. The count variable in Fig. 8.14 will be reset to zero when
moving to the next state after a timeout.
Listing 8.6 is a Verilog program that implements the state diagram in Fig. 8.14
and its simulation is shown in Fig. 8.15. Because we need a counter for the delay count it
is more convenient in this case to combine the state register and combinational modules
C1 in the Moore machine in Fig. 8.3 into a single sequential always block as shown in
Listing 8.6. Note in this case we use only a single state variable.
To generate the 3 Hz signal we will use the version of clkdiv shown in Listing 8.7.
The top-level Verilog program is given in Listing 8.8.