26-04-2012, 11:20 AM
Transistor and Circuit Design Optimization for Low-Power CMOS
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Introduction
Transistor scaling has been a highly successful method for
Silicon technology
■ CMOS technology scaling has now moved to a power constrained condition.
■ Circuit techniques to reduce chip standby leakage has
become a key enabler
■ Scaling is a trading off performance and leakage
■ Different circuit design techniques to optimize the delay and leakage are discussed in this paper.
■ Along with continued scaling, hybrid materials and new process technologies are also recent research interest to balance leakage and delay.
Discussions
Transistor Scaling
A. Power Supply Voltage & Gate-Oxide Thickness
B. Drive Current and Performance
C. Structural and Material Fundamental Limits and
Implications
2. Circuit Design for Leakage - and Active-Power Management
A. Active-Power management
B. Leakage-Power management
C. Multi-Vt Transistors
D. Power-Supply Voltage Scaling
E. Transistor Stacking and Power-supply Gating
F. Dynamic Body Biasing
G. Non-minimum Channel Length
Transistor Scaling
Power Supply Voltage & Gate-Oxide Thickness:
■ VDD was kept constant at 5V from 2 -um to 0.5- um technology
• Continued geometrical scaling resulted very high electric field, power
dissipation, raised performance concerns.
■ VDD and Vt tend to scale by same factor to limit drive-current degradation
• But Vt scaling results in an exponential increase of the OFF-state leakage
and therefore standby power. As a result,
■ Technology scaling has driven in an increase of the gate-dielectric nominal operating fields.
■ Exponential increasing of gate tunneling current has prevented any significant gate-dielectric scaling since 90-nm node.
Conclusions
Standby leakage and active power have become the key issue of continued CMOS transistor scaling.
■ For low-power design, one needs to consider energy dissipation, speed, area, and design–time.
■ Good design is required in trading off performance and leakage.
■ This paper reviewed circuit design techniques and the corresponding implications on transistor optimization from the leakage and active-power management perspective.