11-05-2012, 10:43 AM
Trends in Low-Power VLSI Design
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Introduction
As advances in lithography and fabrication of the N-type metal
oxide superconductor (NMOS) technology became possible in
the 1970s, the bipolar digital logic, transistor-transistor logic
(TTL) lost the battle in the digital design world for exactly the
same reasons that caused older technologies, such as the
vacuum tube technology, to retire. Circuits implemented in
the NMOS technology outperformed the corresponding TTL
circuits in terms of power dissipation. One of the main aspects
of power consumption is that it puts an upper limit on the
number of gates that can be reliably integrated on a single
package for any technology. As technology advanced, chips
grew, and it was possible to integrate more functions into
one chip. Just as for TTL, newer technology, called CMOS,
threatened to replace NMOS in the 1980s because CMOS
proved to consume even less power.
Importance of Low-Power CMOS Design
With advances in CMOS technology, the potential packing
densities increase as the feature size of the MOS devices
shrinks, as shown in Figure 5.1. These increases and decreases
validate what Gordon Moore once said in the 1960s: the
number of transistors that can be integrated on a single die
would grow exponentially with time (Moore, 1965). The
example that amazingly proved his visionary prediction is
best illustrated by tracking the historical evolution of integrated
circuit (IC) design in the company he founded in
1972, Intel, and by using the trends in memory evolution.
Such observations are evident in Figure 5.2. Figure 5.2(A)
shows the trend in the IC logic complexity evolution for Intel
processors in the last two decades, whereas Figure 5.2(B) shows
the memory integration density as a function of time.
Dynamic Power Dissipation
The dynamic power dissipation is the power required for the
circuit to perform its anticipated tasks. In other words, it is the
power needed for charging and discharging all nodes in a
CMOS circuit. This power is only consumed when the circuit
input signals change. In CMOS circuits, the dyanmic power
dominates the total power dissipation. Such characteristic is
greatly affected by current processes or the deep sub-micron
processes (DSM), for which the ratio of leakage power to
dynamic power is increasing. More details about this issue
are presented in Subsection 5.3.3. Dynamic power dissipation
is illustrated in Figure 5.9 for a simple static CMOS inverter.
When the input signal falls, the PMOS transistor switches on
while the NMOS transistor switches off, creating a path from
the supply voltage to the output capacitance, thus allowing the
output load to charge up to the supply Voltage. On the other
hand, when the input signal rises, the opposite scenario occurs:
the NMOS transistor switches on, and the PMOS transistor
switches off, creating a direct path from the output load to
ground and allowing the output load to discharge.
Short Circuit Power Dissipation
The dynamic power dissipation equation is derived usually
by assuming that the inputs have zero rise and fall times,
or, in other words, that the NMOS and PMOS devices are
never on simultaneously. But in reality, such assumption is
not valid, and input signals have nonzero rise and fall times;
hence, a direct current path exists between Vdd and GND
for a short period of time during input switching, in which
case the PMOS and the NMOS devices are simultaneously
conducting. This power component is consumed without
attributing to the circuit behavior; thus, it is considered
redundant.