06-10-2012, 04:03 PM
UART (Universal Asynchronous Receiver Transmitter)
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Introduction
A UART(Universal Asynchronous Receiver Transmitter) is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral deviceserial port . UARTs are now commonly included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).
The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. A UART is used to convert the transmitted information between its sequential and parallel form at each end of the link. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms.
The UART usually does not directly generate or receive the external signals used between different items of equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels.
External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically, the presence or absence of current (in current loops) was used in telegraph circuits.
UART Functionality
The UART is a universal asynchronous receiver/transmitter, which is modeled on the real-world 8251 peripheral interface adapter part. In the model we are considering, the UART consists of three main blocks.
• a serial transmit block
• a serial receive block and
• a CPU Interface (I/F) block.
The serial transmit block has two buffers (FIFO) into which data is written by the CPU I/F block. After the data is written into the buffers it is transmitted serially onto TXD. As long as the FIFO is not full the serial transmit block sets the signal TX_RDY high. The serial receive block has four buffers (FIFO). The block checks for the parity and the validity of the data frame on the RXD input and then writes correct data into its buffers. It also sets the signal RX_RDY low if its FIFO is empty.
Serial Receive Block
This component is responsible for serial receiving of data on RXD. It generates the requisite control signals for reading and writing the receive FIFO. This component can be further divided into sub-components to make modeling easier. The block diagram for this is given below .
All the sub-components have XCS1 as chip enable and XRST as reset signals. The receive clock counter counts the CLK16M clock cycles. It at first counts upto 8 clock cycles when the start bit is received. It then starts counting and sets the srb_clk16 high after every 16 clock cycles. This signal is used as a clock by the transmit data counter,transmit parity counter, and the transmit block. The transmit data counter keeps count of the number of data bits received from rx_d. The data count is incremented when srb_dci is asserted and cleared when srb_dcc is asserted. These signals are provided by the receive control block. The parity counter counts the number of bits that were high in the eight bits of data being recieved. The parity count is incremented on assertion of srb_pci and cleared on assertion of srb_pcc. These two signals are provided by the receive block.