26-06-2012, 11:30 AM
Sequential Multiplier
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This chapter discusses the design, simulation and prototyping of a sequential
multiplier. The multiplication process will be done by the shift-and-add
sequential multiplication procedure. After a discussion of the multiplication
method used, we present the details and interfacing of our design. Then the
multiplier will be partitioned into its data and control parts, and each part will
be designed separately. The completed design will be simulated in Verilog and
tested by programming the FLEX 10K device of the UP2 board.
Sequential Multiplier Specification
The project is the design of a 2-bit sequential multiplier, with 8-bit A and B
inputs and a 16-bit result. The block diagram of the circuit to be designed is
shown in Figure 11.1. This multiplier has an 8-bit bi-directional I/O for
inputting its A and B operands, and outputting its 16-bit output one byte at a
time.
Multiplication begins with the start pulse, and the databus will contain
operands A and B in two consecutive clock pulses. After accepting these data
inputs, the multiplier begins its multiplication process and when it is
completed, it starts sending the result out on the databus. When the leastsignificant
byte is placed on databus, the Lsb_out output is issued, and for the
most-significant byte, msb_out is issued. When both bytes are outputted, done
becomes 1, and the multiplier is ready for another set of data.
The multiplexed bi-directorial databus is used to reduce the total number of
pins of the multiplier.
Shift-and-Add Multiplication
When designing multipliers there is always a compromise to be made between
how fast the multiplication process is done and how much hardware we are
using for its implementation.
A simple multiplication method that is slow, but efficient in use of hardware
is the shift-and-add method. In this method, depending on bit i of operand A,
either operand B is added to the collected partial result and then shifted to the
right (when bit i is 1), or (when bit i is 0) the collected partial result is shifted
one place to the right without being added to B.
This method is justified by considering how binary multiplication is done
manually. Figure 11.2 shows manual multiplication of two 8-bit binary
numbers.
Control Data Partitioning
The multiplier has a datapath and a controller. The data part consists of
registers, logic units and their interconnecting busses. The controller is a state
machine that issues control signals for control of what gets clocked into the
data registers.
As shown in Figure 11.4, the data path registers and the controller are
triggered with the same clock signal. On the rising edge of a clock the
controller goes into a new state. In this state, several control signals are issued,
and as a result the components of the datapath start reacting to these signals.
The time given for all activities of the datapath to stabilize is from one edge of
the clock to another. Values that are propagated to the inputs of the datapath
registers are clocked into these register with every clock edge.