14-05-2014, 03:53 PM
VHDL CODE
1370340697-VHDLCODEFORUART (1).docx (Size: 264.87 KB / Downloads: 13)
VHDL CODE FOR TRANSMITTER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
Port ( datain : in STD_LOGIC_vector(7 downto 0);
txd : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end transmitter;
architecture Behavioral of transmitter is
signal temp td_logic_vector(7 downto 0);
signal address td_logic_vector(3 downto 0);
begin
process(clk,datain)
begin
if(rst='1') then
temp<="00000000";
txd<='1';
address<="0000";
elsif(clk'event and clk='1') then
temp<=datain;
if temp/="UU" THEN
case address is
when "0000" =>
txd<= '0';
address<= address + "0001";
when "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" |
"0111" | "1000" =>
txd<= temp(0);
temp<= '1' & temp(7 downto 1);
address<= address + "0001";
when "1001" =>
txd<= '1';
temp<= '1' & temp(7 downto 1);
address<= "0000";
when others =>
null;
end case;
end if;
end if;
end process;
end Behavioral;
This is the VHDL code for transmitter which transmits the required data to the receiver
VHDL CODE FOR RECIEVER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity receiver is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rxd : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR (7 downto 0));
end receiver;
architecture Behavioral of receiver is
signalreceiver_shift_register td_logic_vector(7 downto 0);
signal address td_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if(rst='1')then
dataout<="11111111";
address<="0000";
elsif(clk'event and clk='1') then
case address is
when "0000" =>
ifrxd = '0' then
address<= address + "0001";
end if;
when "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" |
"0111" | "1000" =>
address<= address + "0001";
receiver_shift_register<= rxd&receiver_shift_register(7 downto 1);
when "1001" =>
address<= "0000";
when others => null;
end case;
dataout<=receiver_shift_register;
end if;
end process;
end Behavioral;
This is the VHDL code for UART receiver which receives the data from transmitter. These are compiled and then given stimulation. These are stimulated and outputs are seen in stimulation
.STIMULATION
The VHDL simulator reads VHDL description compiles it in to an internal format, and then executes the compiled format using test vectors, after compilation if any syntax errors are there they has to be removed and recompiled. After analyzing the results of the simulation stimulus for the design has to be added. This may be file of input stimulus design (or) the file output stimulus design using waveform editor the respective output waveform are to be observed to test the functionality of the design
Stimulation output for transmitter