12-09-2013, 02:21 PM
VHDL CODING STYLE AND PROGRAMING CONCEPT
CODING STYLE AND PROGRAMING .doc (Size: 183.5 KB / Downloads: 20)
ABSTRACT
SEMINAR ON VHSIC Hard ware Description Language(VHDL) :VHDL Stands for Very High Speed Integrated Circuits Hard ware Description Language.VHDL used in electronic design automation to describe and simulate complex digital systems.VHDL is designed and developed by department of US defense . The first version of VHDL designed to IEEE Standard 1076-1987 which include wide range of data types like numerical,logical,character,array and time.next the IEEE Standard 1164 which defined 9 value logic type.next the updated IEEE standard that allows the syntax more consistence and provide naming flexibility ,extends character type to allowing ISO-8859-1 printable characters and also add the xnor operator .Next IEEE Standard 1076.2 added the better handling functionalities of real and complex data types.IEEE Standard 1076.3 allows signed and unsigned types.IEEE standard 1076.1 provides analog and mixed signal circuit design extensions.
VHDL CODING STYLE AND PROGRAMMING CONCEPT
VHDL is hardware description language that can be used to model a digital system.The digital system can be simple as logic gate or as complex as a complete electronic system.To describe a digital system,VHDL provides two different types of primary constructor called design units.
ARCHITECTURAL BODY
It describes the internal description of design or it tell what is there inside design.Each entity has at least one or more architecture.Architecture can be described using structural,dataflow,behavioural or mixed style.Architecture can be used to describe at different levels of abstraction like gate level,register transfer level(RTL) or behaviour level.
Dataflow modelling
In the style of modelling,the internal working of an entity can be implemented using concurrent signal assignment.
The architecture body consists of concurrent signal assignment(s<=a and B)which describes the functionality of the design.whenever there is a change in RHS,the expression is evaluated and the value is assigned to LHS.
Structural modelling:
The implementation of an entity is done through set of interconnected components.It contain:
Signal declaration
Component instances
Port maps.
Wait statements.
Before instantiating the component it should be declared using component declaration as shown above.Component declaration declaration yhe name of the entity and interface of a component.
Let’s try to understand this by taking the example of full adder using 2 half adder and 1 OR gate.
CONCLUSION
Using VHDL programming we candesign any circuit from gate level toprocessor level. It is easy to learn and highcapability with software. Using VHDL programming we candesign any circuit from gate level to processor level. It is easy to learn and highcapability with software.