14-02-2013, 10:40 AM
VHDL Coding Basics
VHDL.ppt (Size: 1.16 MB / Downloads: 67)
VHDL features
Case insensitive
inputa, INPUTA and InputA are refer to same variable
Comments
until end of line
If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line
Statements are terminated by
Signal assignment:
User defined names:
letters, numbers, underscores (‘_’)
start with a letter
Design using VHDL
Define the logic function
output inputa and inputb;
output is assigned to be inputa AND inputb
LHS contains only 1 variable only
RHS can be logics operations for many variables
VHDL language abstractions
VHDL is rich in language abstractions, in addition to which the language can be used to describe different abstraction levels, from functions right down to a gate description
Abstraction levels are a means of concealing details
Definitions of the Description Methods
Structural Description Method: expresses the design as an arrangement of interconnected components
It is basically schematic
Behavioral Description Method: describes the functional behavior of a hardware design in terms of circuits and signal responses to various stimuli
The hardware behavior is described algorithmically
Data-Flow Description Method: is similar to a register-transfer language
This method describes the function of a design by defining the flow of information from one input or register to another register or output
Behavioral level
Behavior and time are described at this level
No architecture is required here
The advantage of models at this level is that models for simulation can be built quickly
A behavioral model can be described as functional modules and an interface between them
The modules contain one or more functions and time relations
In certain cases the architecture can be defined
Synthesis = Increasing Complexity
Synthesis is done between each level
The volume of information increases between the various abstraction levels
E.g. technology information is required to synthesize from RT to gate level
Each transition (synthesis) generates more information
In order to implement a function in an ASIC, are required the followings:
technology information
wiring information
gate information
set-up times
Object-based language
Staying with computer science a while longer, VHDL is an object-based language, i.e. what separates VHDL from object-oriented languages is that the language does not have inheritance
Generic components and instantiation are typical for object-based languages
Generic components are components which can be modified before instantiation, e.g. a generic component which copes with different width for the input and output signals