Reversible logic is one of the emerging technologies that have promising applications in quantum computing. This project will deal with the design of a 16-bit Reversible Logic Arithmetic Unit (ALU) with 15 operations that is presented using the Double Peres gate, the Fredkin gate, the Toffolli gate, the DKG gate and the NOT gate. A new VLSI architecture for ALU is proposed using reversible logic gates. ALU is one of the most important components of the CPU that can be part of a programmable reversible computing device, such as a quantum computer. A first single-bit reversible ALU and a second single-bit ALU are designed and then 16 single-bit ALUs are cascaded by carrying out the execution of the ALU performing the LSB operation as input to carry out the ALU that performs the following LSB operation. The design is implemented and verified in Verilog in modelsim Altera 6.6d.
An important requirement of a digital system design is to reduce power dissipation. Reversible logic is an emerging technique, which has the ability to reduce energy dissipation. Reversible circuits do not lose information and can generate single outputs from specified inputs and vice versa. There is no loss of bits during its calculation, resulting in a reduction of power dissipation. In this work, an 8-bit arithmetic and logic unit (ALU) is proposed and designed using reversible logic circuits in Verilog HDL. The result of the synthesis and implementation show that the proposed ALU improves 39% in terms of power dissipation and 10% in terms of propagation delay on the ALU using conventional circuits. It has applications in various fields, such as the design of low-power complementary metal oxide (CMOS) semiconductors, optical information processing, cryptography, quantum computing and nanotechnology.