03-05-2013, 04:53 PM
VHDL Quick Start
VHDL Quick.pdf (Size: 110.87 KB / Downloads: 14)
Objective
• Quick introduction to VHDL
– basic language concepts
– basic design methodology
• Use The Student’s Guide to VHDL
or The Designer’s Guide to VHDL
– self-learning for more depth
– reference for project work
Modeling Digital Systems
• VHDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost and
time
– avoid design errors!
Modeling Behavior
• Architecture body
– describes an implementation of an entity
– may be several per entity
• Behavioral architecture
– describes the algorithm performed by the module
– contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements
Modeling Structure
• Structural architecture
– implements the module as a composition of subsystems
– contains
• signal declarations, for internal interconnections
– the entity ports are also treated as signals
• component instances
– instances of previously declared entity/architecture pairs
• port maps in component instances
– connect signals to component ports
• wait statements
Mixed Behavior and Structure
• An architecture can contain both behavioral and
structural parts
– process statements and component instances
• collectively called concurrent statements
– processes can read and assign to signals
• Example: register-transfer-level model
– data path described structurally
– control section described behaviorally
Analysis
• Check for syntax and semantic errors
– syntax: grammar of the language
– semantics: the meaning of the model
• Analyze each design unit separately
– entity declaration
– architecture body
– …
– best if each design unit is in a separate file
• Analyzed design units are placed in a library
– in an implementation dependent internal form
– current library is called work
Elaboration
• “Flattening” the design hierarchy
– create ports
– create signals and processes within architecture body
– for each component instance, copy instantiated entity
and architecture body
– repeat recursively
• bottom out at purely behavioral architecture bodies
• Final result of elaboration
– flat collection of signal nets and processes
Simulation Algorithm
• Simulation cycle
– advance simulation time to time of next transaction
– for each transaction at this time
• update signal value
– event if new value is different from old value
– for each process sensitive to any of these events, or
whose “wait for … ” time-out has expired
• resume
• execute until a wait statement, then suspend
• Simulation finishes when there are no further
scheduled transactions